Re: [PATCH v1 3/6] dt-bindings: display: tegra: Document 8-bit CPU parallel interface

[Thierry Reding <thierry.reding@kernel.org>]

[-- Attachment #1: Type: text/plain, Size: 5110 bytes --]

On Wed, Sep 30, 2026 at 12:52:18PM +0300, Svyatoslav Ryhel wrote:
> ср, 30 вер. 2026 р. о 12:19 Mikko Perttunen <mperttunen@nvidia.com> пише:
> >
> > On Wednesday, September 30, 2026 4:05 PM Svyatoslav Ryhel wrote:
> > > Document 8-bit CPU parallel MIPI DBI Type B interface provided by
> > > Tegra20/30 SoCs display controller.
> > >
> > > Signed-off-by: Svyatoslav Ryhel <clamor95@gmail.com>
> > > ---
> > >  .../display/tegra/nvidia,tegra-8bit-cpu.yaml  | 138 ++++++++++++++++++
> > >  1 file changed, 138 insertions(+)
> > >  create mode 100644 Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> > >
> > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> > > new file mode 100644
> > > index 0000000000000..f0dab608b2936
> > > --- /dev/null
> > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegra-8bit-cpu.yaml
> > > @@ -0,0 +1,138 @@
> > > +# SPDX-License-Identifier: (GPL-2.0-only OR BSD-2-Clause)
> > > +%YAML 1.2
> > > +---
> > > +$id: http://devicetree.org/schemas/display/tegra/nvidia,tegra-8bit-cpu.yaml#
> > > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > > +
> > > +title: Nvidia Tegra DC based MIPI DBI Type B bridge
> > > +
> > > +maintainers:
> > > +  - Svyatoslav Ryhel <clamor95@gmail.com>
> > > +
> > > +description: The display controller in Tegra20/30 SoCs features an
> > > +  8-bit SPI interface that closely resembles the MIPI DBI Type B
> > > +  protocol and is referred to as '8-bit CPU'. Each display controller
> > > +  provides two such interfaces, which can be used to send MIPI DCS
> > > +  commands to initialize and control the panel while image data is
> > > +  transmitted via 16/18/24-line RGB.
> > > +
> > > +properties:
> > > +  compatible:
> > > +    const: nvidia,tegra-8bit-cpu
> > > +
> > > +  dc-gpios:
> > > +    description: Data/command selection pin.
> > > +    maxItems: 1
> > > +
> > > +  rw-gpios:
> > > +    description: Read/write pin.
> > > +    maxItems: 1
> > > +
> > > +  cs-gpios:
> > > +    description: Chip select pin.
> > > +    maxItems: 1
> > > +
> > > +  data-gpios:
> > > +    description: Specifies a set of 8 gpio pins used to transfer data.
> > > +    minItems: 8
> > > +    maxItems: 8
> >
> > Based on my admittedly brief research, according to the TRM the display
> > controller can drive all of these pins - of which there are two fixed
> > sets as you mention - directly. So we'd need to describe which interface
> > the display is connected to in DT, but not any GPIOs (which they really
> > aren't).
> >
> 
> I am perfectly fine to not expose any gpios in the binding, if this is
> preferred. Only question, which method of interface checking would be
> preferred. I assume if primary then nothing, if secondary - boolean
> prop "nvidia,secondary"? Feel free to share your vision.

The driver currently uses the GPIOs to program DBI commands, so I
suspect we do need some way of controlling those pins. Or is there a way
to have the display controller program the pins and send commands? That
would be much preferred because it would more accurately reflect the HW
design and possibly also simplify the driver because it doesn't need to
parse the GPIOs and then also not use the GPIO API to set the values.

As for selecting the interface to use, it could probably be just a
simple, single-cell value with two valid values. That's a bit clearer
than a boolean, because with a boolean you need to explicitly document
what happens when it is absent.

> > > +
> > > +  nvidia,init-sequence:
> > > +    $ref: /schemas/types.yaml#/definitions/uint32-array
> > > +    description: Device specific set of values used in DC DISP_SPI_INIT_SEQ
> > > +      registers.
> > > +    minItems: 4
> > > +    maxItems: 4
> >
> > And AIUI this is panel-specific DBI commands the display controller will
> > transmit. So ideally the display driver should receive this data from
> > the panel driver.
> >
> 
> This is not panel driver data, but it is panel or maybe even more
> interface itself specific. TRM has no clear method of generation of
> this seq I am aware of. Maybe I have missed smth. These 4 entries
> co-respond to DC_DISP_SPI_INIT_SEQ_DATA_A_0,
> DC_DISP_SPI_INIT_SEQ_DATA_B_0, DC_DISP_SPI_INIT_SEQ_DATA_C_0 and
> DC_DISP_SPI_INIT_SEQ_DATA_D_0 registers of DC. Maybe you have some
> info to shed some light onto method of generation of this seq. Then it
> could be simply removed from binding and calculated internally. Thank
> you!

Even if this is interface-specific data, it is still defined by the
panel that's being used, right?

As such it'd make sense to integrate it into the panel driver and have
some side-channel to feed it to the display controller. If there's no
good standard way of doing so, having the display controller read it
from the panel node and programming it at the appropriate time could
work, too.

Thierry

[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 833 bytes --]