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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-3537ca6d202sm37060349eec.13.2026.10.12.20.08.58 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Mon, 12 Oct 2026 20:09:03 -0700 (PDT) Date: Tue, 13 Oct 2026 11:08:56 +0800 From: Shawn Guo To: Taniya Das Cc: Bjorn Andersson , Michael Turquette , Stephen Boyd , Brian Masney , Bartosz Golaszewski , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Neil Armstrong , Konrad Dybcio , Ajit Pandey , Imran Shaik , Jagadeesh Kona , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, Konrad Dybcio , Alexandre Mergnat Subject: Re: [PATCH v3 2/6] clk: qcom: negcc-nord: keep GPU2 CFG clock enabled via critical CBCR Message-ID: References: <20260724-nords_mm_v1-v3-0-32b45232217f@oss.qualcomm.com> <20260724-nords_mm_v1-v3-2-32b45232217f@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260724-nords_mm_v1-v3-2-32b45232217f@oss.qualcomm.com> X-Proofpoint-GUID: R0skzn-_DxpRmZCJxAKpMQm00voH9iab X-Proofpoint-Spam-Info: AW1haW4tMjYxMDEzMDAxMiBTYWx0ZWRfXy42sIdetSgnc Vow4HBIyXL/3WMbWJioR8yDAAufyvM1Z6tWOEPuCKJyZenlzx4bDyOJKKm6yxolTr7fD9VHRGgx 42GofAe6DRWinUrIbgJ7pw+I5IJk7Fg= X-Proofpoint-ORIG-GUID: R0skzn-_DxpRmZCJxAKpMQm00voH9iab X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDEzMDAxMiBTYWx0ZWRfXyjnpZL8aSPJW w4mAbFQLBhJYFjSvL/TWpsyBlvSdKM7hBVHkXjx/nkLLzWPnpRWoWH5Equ8uJKtjdzanaVXQGN/ pMTAbYcSzhw2VNIIGokQ6bwS+ODg2ULiiXLt0Gh8CSA9mCD1tyUkjgUaR1ELiEWkzQgKMT+1vcS jPou4XLZaAX2pvEPvsKGlOkaj1+1ec2gqZiFVIIKknsKxEhPB3vQS3K7TQpq+3EHcBxta9+4GUK zfZDcwo93vVrbNjIm0+M5pG/sx3BuJv6bDq9OBThtsKJNVbbOLL3aTX8nnr19fjXzn3bK1wxkzd SBO6aHNCoP2OohxXOrxAdgo0MGulmLhFYoVsNVyHUZtYTedyFcahx6VmlNP8zoq0+My0ZsKbtBE xGk2IGTmdlSl62UynoCsjsMEVIH6cLjRkArcQ86yokNws3s9E5IAYnKzzYtzVvjWn0fswJrRRGG IHrQwteVrDSFm7pbpLw== X-Authority-Analysis: v=2.4 cv=PbhqFShd c=1 sm=1 tr=0 ts=6acda0d1 cx=c_pps a=wEP8DlPgTf/vqF+yE6f9lg==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=DJpcGTmdVt4CTyJn9g5Z:22 a=EUspDBNiAAAA:8 a=IpJZQVW2AAAA:8 a=yUjrznqbfBiV5e72-0MA:9 a=CjuIK1q_8ugA:10 a=bBxd6f-gb0O0v-kibOvt:22 a=IawgGOuG5U0WyFbmm1f5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-13_01,2026-10-09_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 lowpriorityscore=0 bulkscore=0 clxscore=1015 impostorscore=0 spamscore=0 phishscore=0 suspectscore=0 priorityscore=1501 malwarescore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610080000 definitions=main-2610130012 On Fri, Jul 24, 2026 at 04:25:06PM +0530, Taniya Das wrote: > The GPU2 CFG clock must remain enabled for correct operation and > should not be exposed as a controllable clk_branch. Hi Taniya, Could you share a bit more information why this is the case? I do not seem to get any problem when testing without this change. Shawn > > Remove the clk_branch and mark its CBCR as critical instead to > prevent unintended gating. This follows the same approach as > 'nw_gcc_gpu_cfg_ahb_clk' and aligns with other always-on clocks in > Qualcomm CC drivers. > > Fixes: a4f780cd5c7a ("clk: qcom: gcc: Add multiple global clock controller driver for Nord SoC") > Reviewed-by: Konrad Dybcio > Reviewed-by: Alexandre Mergnat > Signed-off-by: Taniya Das > --- > drivers/clk/qcom/negcc-nord.c | 22 ++++++---------------- > 1 file changed, 6 insertions(+), 16 deletions(-) > > diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c > index 2e653ef0fe0e304f09ed354d5578fdbed9151d20..bc4d478d5606ad7478431573f98b62f6f9b7d9fb 100644 > --- a/drivers/clk/qcom/negcc-nord.c > +++ b/drivers/clk/qcom/negcc-nord.c > @@ -952,21 +952,6 @@ static struct clk_branch ne_gcc_gp2_clk = { > }, > }; > > -static struct clk_branch ne_gcc_gpu_2_cfg_clk = { > - .halt_reg = 0x34004, > - .halt_check = BRANCH_HALT_VOTED, > - .hwcg_reg = 0x34004, > - .hwcg_bit = 1, > - .clkr = { > - .enable_reg = 0x34004, > - .enable_mask = BIT(0), > - .hw.init = &(const struct clk_init_data) { > - .name = "ne_gcc_gpu_2_cfg_clk", > - .ops = &clk_branch2_ops, > - }, > - }, > -}; > - > static struct clk_branch ne_gcc_gpu_2_gpll0_clk_src = { > .halt_check = BRANCH_HALT_DELAY, > .clkr = { > @@ -1817,7 +1802,6 @@ static struct clk_regmap *ne_gcc_nord_clocks[] = { > [NE_GCC_GPLL0] = &ne_gcc_gpll0.clkr, > [NE_GCC_GPLL0_OUT_EVEN] = &ne_gcc_gpll0_out_even.clkr, > [NE_GCC_GPLL2] = &ne_gcc_gpll2.clkr, > - [NE_GCC_GPU_2_CFG_CLK] = &ne_gcc_gpu_2_cfg_clk.clkr, > [NE_GCC_GPU_2_GPLL0_CLK_SRC] = &ne_gcc_gpu_2_gpll0_clk_src.clkr, > [NE_GCC_GPU_2_GPLL0_DIV_CLK_SRC] = &ne_gcc_gpu_2_gpll0_div_clk_src.clkr, > [NE_GCC_GPU_2_HSCNOC_GFX_CLK] = &ne_gcc_gpu_2_hscnoc_gfx_clk.clkr, > @@ -1946,10 +1930,16 @@ static void clk_nord_regs_configure(struct device *dev, struct regmap *regmap) > qcom_branch_set_force_mem_core(regmap, ne_gcc_ufs_phy_axi_clk, true); > } > > +static const u32 ne_gcc_nord_critical_cbcrs[] = { > + 0x34004, /* NE_GCC_GPU_2_CFG_CLK */ > +}; > + > static const struct qcom_cc_driver_data ne_gcc_nord_driver_data = { > .dfs_rcgs = ne_gcc_nord_dfs_clocks, > .num_dfs_rcgs = ARRAY_SIZE(ne_gcc_nord_dfs_clocks), > .clk_regs_configure = clk_nord_regs_configure, > + .clk_cbcrs = ne_gcc_nord_critical_cbcrs, > + .num_clk_cbcrs = ARRAY_SIZE(ne_gcc_nord_critical_cbcrs), > }; > > static const struct qcom_cc_desc ne_gcc_nord_desc = { > > -- > 2.34.1 > >