Re: [PATCH v3 8/8] PCI/quirks: Avoid certain address on Genoa systems

[Andy Shevchenko <andriy.shevchenko@intel.com>]

On Tue, Oct 13, 2026 at 09:41:48PM -0500, Mario Limonciello wrote:
> On 10/13/26 19:43, Borislav Petkov wrote:
> > On Tue, Oct 13, 2026 at 05:40:10PM -0500, Bjorn Helgaas wrote:
> > > But I'm frankly terrified to touch it because I'm skeptical that two
> > > more quirks are enough.  I just expect that whatever strategy BIOS
> > > uses to build these maps is likely to be used on many models.  I do
> > 
> > Do we have an explanation why BIOS is doing that shit?
> > 
> > Mario?
> 
> If I was to guess; because Windows allocates MMIO space differently it
> hasn't been a problem.

Oh, I can confirm this part as I noticed the issue on 64-bit addresses for
Intel LPSS at some point exactly due to different ways of allocating space for
the devices for PCI. Id est one is goes upwards (from the start to the end of
the region), while the other downwards (from the end to the start of the
region).

> Which begs the question; does Ilpo's series improve things enough that we
> wouldn't have these problems either?
> 
> Maybe we should just tail my patches on Ilpos' series and then land them
> linux-next the very beginning of next cycle and beg everyone who was
> affected to test linux-next.
> 
> > Btw, Mario, you should replace "Genoa" with "Zen4" everywhere so that it is
> > more clear to people.
> 
> Ack; if I send mine out on their own I'll adjust.

-- 
With Best Regards,
Andy Shevchenko