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Fri, 02 Oct 2026 12:50:38 -0700 (PDT) Date: Fri, 2 Oct 2026 15:50:34 -0400 From: Brian Masney To: Changhuang Liang Cc: Michael Turquette , Jerome Brunet , Stephen Boyd , Philipp Zabel , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Emil Renner Berthing , Kees Cook , "Gustavo A . R . Silva" , Richard Cochran , linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org, devicetree@vger.kernel.org, linux-riscv@lists.infradead.org, linux-hardening@vger.kernel.org, netdev@vger.kernel.org, Hal Feng Subject: Re: [PATCH v5 10/23] clk: starfive: Add JHB100 System-2 clock generator driver Message-ID: References: <20260930124317.5648-1-changhuang.liang@starfivetech.com> <20260930124317.5648-11-changhuang.liang@starfivetech.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260930124317.5648-11-changhuang.liang@starfivetech.com> User-Agent: Mutt/2.4.2 (2026-08-30) Hi Changhuang, On Wed, Sep 30, 2026 at 05:43:04AM -0700, Changhuang Liang wrote: > Add support for JHB100 System-2 clock generator (SYS2CRG). > > Signed-off-by: Changhuang Liang > --- > drivers/clk/starfive/Kconfig | 10 ++ > drivers/clk/starfive/Makefile | 1 + > .../clk/starfive/clk-starfive-jhb100-sys2.c | 129 ++++++++++++++++++ > 3 files changed, 140 insertions(+) > create mode 100644 drivers/clk/starfive/clk-starfive-jhb100-sys2.c > > diff --git a/drivers/clk/starfive/Kconfig b/drivers/clk/starfive/Kconfig > index 11da8bcc4046..cfaac934a8e0 100644 > --- a/drivers/clk/starfive/Kconfig > +++ b/drivers/clk/starfive/Kconfig > @@ -92,3 +92,13 @@ config CLK_STARFIVE_JHB100_SYS1 > help > Say yes here to support the system-1 clock controller on the > StarFive JHB100 SoC. > + > +config CLK_STARFIVE_JHB100_SYS2 > + bool "StarFive JHB100 system-2 clock support" > + depends on ARCH_STARFIVE || COMPILE_TEST > + select CLK_STARFIVE_JH71X0 > + select RESET_STARFIVE_JHB100 if RESET_CONTROLLER > + default ARCH_STARFIVE > + help > + Say yes here to support the system-2 clock controller on the > + StarFive JHB100 SoC. > diff --git a/drivers/clk/starfive/Makefile b/drivers/clk/starfive/Makefile > index 0061550e0f7e..29cdef20575e 100644 > --- a/drivers/clk/starfive/Makefile > +++ b/drivers/clk/starfive/Makefile > @@ -13,3 +13,4 @@ obj-$(CONFIG_CLK_STARFIVE_JH7110_VOUT) += clk-starfive-jh7110-vout.o > > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS0) += clk-starfive-jhb100-sys0.o > obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS1) += clk-starfive-jhb100-sys1.o > +obj-$(CONFIG_CLK_STARFIVE_JHB100_SYS2) += clk-starfive-jhb100-sys2.o > diff --git a/drivers/clk/starfive/clk-starfive-jhb100-sys2.c b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c > new file mode 100644 > index 000000000000..a2c7e8eba9b6 > --- /dev/null > +++ b/drivers/clk/starfive/clk-starfive-jhb100-sys2.c > @@ -0,0 +1,129 @@ > +// SPDX-License-Identifier: GPL-2.0 > +/* > + * StarFive JHB100 System-2 Clock Driver > + * > + * Copyright (C) 2024 StarFive Technology Co., Ltd. > + * > + * Author: Changhuang Liang > + * > + */ > + > +#include > +#include > +#include > + > +#include "clk-starfive-jh71x0.h" > + > +#define JHB100_SYS2CLK_NUM_CLKS (JHB100_SYS2CLK_MAIN_ICG_EN_JTAG1 + 1) > + > +/* external clocks */ > +#define JHB100_SYS2CLK_OSC (JHB100_SYS2CLK_NUM_CLKS + 0) > +#define JHB100_SYS2CLK_PLL1 (JHB100_SYS2CLK_NUM_CLKS + 1) > +#define JHB100_SYS2CLK_GPU0_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 2) > +#define JHB100_SYS2CLK_GPU1_NCNOC_INIT (JHB100_SYS2CLK_NUM_CLKS + 3) > + > +static const char * const jhb100_sys2_ext_clk[] = { > + "osc", > + "pll1", > + "gpu0_ncnoc_init", > + "gpu1_ncnoc_init", > +}; > + > +static const struct jh71x0_clk_data jhb100_sys2crg_clk_data[] = { > + /* jtag mst*/ > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_HCLK, "jtagm0_hclk", 6, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_HCLK, "jtagm1_hclk", 6, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG, "jtagm0_ATPG", 12, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG, "jtagm1_ATPG", 12, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM0_ATPG_TCLOCK, "jtagm0_atpg_tclock", 2, > + JHB100_SYS2CLK_JTAGM0_ATPG), > + JH71X0__DIV(JHB100_SYS2CLK_JTAGM1_ATPG_TCLOCK, "jtagm1_atpg_tclock", 2, > + JHB100_SYS2CLK_JTAGM1_ATPG), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_HCLK, "jtag0_mst_wrap_hclk", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), Can you leave a comment somewhere about why CLK_IGNORE_UNUSED is on some of these clocks? We may be able to deprecate this flag once some variation of the clk sync_state support lands: https://lore.kernel.org/linux-clk/20260626-clk-sync-state-v1-0-4156d8196dc8@redhat.com/ > + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_CLK_JTAG, "jtag0_mst_wrap_clk_jtag", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_HCLK), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_APB_PCLK, "jtag0_mst_wrap_apb_pclk", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG0_MST_WRAP_ATPG_TCLOCK, "jtag0_mst_wrap_atpg_tclock", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM0_ATPG), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_HCLK, "jtag1_mst_wrap_hclk", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_CLK_JTAG, "jtag1_mst_wrap_clk_jtag", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_HCLK), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_APB_PCLK, "jtag1_mst_wrap_apb_pclk", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), > + JH71X0_GATE(JHB100_SYS2CLK_JTAG1_MST_WRAP_ATPG_TCLOCK, "jtag1_mst_wrap_atpg_tclock", > + CLK_IGNORE_UNUSED, JHB100_SYS2CLK_JTAGM1_ATPG), > + /* hostusbcmn */ > + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSB_NCNOC_TARG, "hostusb_ncnoc_targ", 12, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_HOSTUSBCMN_CFG_500, "hostusbcmn_cfg_500", 4, > + JHB100_SYS2CLK_PLL1), > + /* bmcperiph1 */ > + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_NCNOC_TARG, "bmcper1_ncnoc_targ", 6, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_250, "bmcper1_cfg_250", 5, > + JHB100_SYS2CLK_PLL1), > + JH71X0__DIV(JHB100_SYS2CLK_BMCPER1_CFG_143_DFT, "bmcper1_cfg_143_dft", 8, > + JHB100_SYS2CLK_PLL1), > + JH71X0_GATE(JHB100_SYS2CLK_BMCPER1_CFG_143, "bmcper1_cfg_143", CLK_IS_CRITICAL, Also please leave a comment why CLK_IS_CRITICAL is needed as well for these particular clocks. Brian