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X-CSE-ConnectionGUID: hq/0WWawTzWYojWMBH+3yg== X-CSE-MsgGUID: WL9Fo6F3QKWbMgC5d15F6Q== X-IronPort-AV: E=McAfee;i="6800,10657,11924"; a="91883461" X-IronPort-AV: E=Sophos;i="6.27,138,1787036400"; d="scan'208";a="91883461" Received: from orviesa002.jf.intel.com ([10.64.159.142]) by fmvoesa109.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Oct 2026 08:02:18 -0700 X-CSE-ConnectionGUID: 6IqjmuD1SNyntD6eBjnptQ== X-CSE-MsgGUID: OQgShzM1QFyyGM+kojhAgw== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,138,1787036400"; d="scan'208";a="305961762" Received: from amilburn-desk.amilburn-desk (HELO localhost) ([10.245.245.78]) by orviesa002-auth.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 03 Oct 2026 08:02:15 -0700 Date: Sat, 3 Oct 2026 18:02:12 +0300 From: "andriy.shevchenko@intel.com" To: Kanak Shilledar Cc: "andy@kernel.org" , "robh@kernel.org" , Kernel , "macromorgan@hotmail.com" , "linux-kernel@vger.kernel.org" , "conor+dt@kernel.org" , "joshua.crofts1@gmail.com" , "devicetree@vger.kernel.org" , "jean-baptiste.maneyrol@tdk.com" , "dlechner@baylibre.com" , "nuno.sa@analog.com" , "krzk+dt@kernel.org" , "jic23@kernel.org" , "marcelo.schmitt1@gmail.com" , Henrik Grimler , "linux-iio@vger.kernel.org" Subject: Re: [PATCH v5 5/6] iio: imu: inv_icm42607: Implement MREGx register access Message-ID: References: <20261002-b4-inv_icm42370p-v5-0-c65281b745c9@axis.com> <20261002-b4-inv_icm42370p-v5-5-c65281b745c9@axis.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Fri, Oct 02, 2026 at 02:25:48PM +0000, Kanak Shilledar wrote: > On Fri, 2026-10-02 at 16:12 +0300, Andy Shevchenko wrote: > > On Fri, Oct 02, 2026 at 01:54:29PM +0200, Kanak Shilledar wrote: ... > > > +static int inv_icm42607_mreg_read(struct regmap *map, unsigned int > > > reg, > > > +   u8 *data, size_t count) > > > +{ > > > + unsigned int val; > > > + bool idle_set; > > > + u8 blk_sel; > > > + int ret; > > > + > > > + /* MREG access is one byte per transaction, no burst > > > support. */ > > > + if (count != 1) > > > + return -EINVAL; > > > + > > > + ret = inv_icm42607_blk_sel(reg, &blk_sel); > > > + if (ret) > > > + return ret; > > > + > > > + ret = inv_icm42607_mclk_get(map, &idle_set); > > > + if (ret) > > > + return ret; > > > > > + ret = regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, > > > blk_sel); > > > + if (ret) > > > + goto out; > > > > So, can we use regmap ranges instead? > > We can't use regmap ranges because the register accesses for different > banks guarded by a specific routine of writing the bank selector, the > address pointer and then finally accessing the value along with > checking for timings and clocks. There is also a limitation that, > accessing the registers in banks other than USER BANK 0 can only be > done serially. It doesn't support bulk reads. This is documented in > section 13 of the datasheet [1]. Sorry if I missed it, but this is an important part of the driver design, if not yet, please add a respective note to the commit message on it. > > > + ret = regmap_write(map, INV_ICM42607_REG_MADDR_R, > > > +    FIELD_GET(INV_ICM42607_REG_ADDR_MASK, > > > reg)); > > > + if (ret) > > > + goto out; > > > + > > > + fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US); > > > + > > > + ret = regmap_read(map, INV_ICM42607_REG_M_R, &val); > > > + if (ret) > > > + goto out; > > > + > > > + fsleep(INV_ICM42607_MREG_ACCESS_DELAY_US); > > > + > > > + *data = val; > > > +out: > > > + /* Restore direct access. */ > > > + ret = regmap_write(map, INV_ICM42607_REG_BLK_SEL_R, 0); > > > + inv_icm42607_mclk_put(map, idle_set); > > > + > > > + return ret; > > >  } ... > > > +static const struct regmap_config inv_icm42607_regmap_config = { > > > + .reg_bits = 8, > > > + .val_bits = 8, > > > > No cache? Why? > As the virtual regmap config has some caching for USER BANK 0 registers > only. The indirect banks doesn't support caching [1]. This is strange. You mean they are volatile by definition (HW)? Otherwise if it's just a software issue, it can still be done, for regcache there is no difference if the offset is real or paged. > > > +}; > [1] Datasheet: https://www.lcsc.com/product-detail/C5129967.html -- With Best Regards, Andy Shevchenko