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Sun, 4 Oct 2026 13:20:55 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.126.190.181) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Sun, 4 Oct 2026 13:20:54 -0700 Date: Sun, 4 Oct 2026 13:20:52 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , , Subject: Re: [PATCH v10 03/13] iommu/arm-smmu-v3: Add ARM_SMMU_FEAT_EVTQ for the event queue Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SN1PEPF000397B3:EE_|DS0PR12MB7970:EE_ X-MS-Office365-Filtering-Correlation-Id: 9f866ae4-3db0-41a3-8506-08df2255051f X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|1800799024|7416014|376014|82310400026|23010399003|11063799006|56012099006|4143699003|10067099003|18002099003|22082099003|6133799003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 5sTOE5zCtw2AXDvFX4TriSn+7bTaQgEjU4/RtMx8ME7OHL0wl/iSPp/QmPcFTxD3ntCpAQo1xgcaypSwGT8Vw4xBs2qj4UqduRRx/usDffvebLxD/gG6JHUqBJPqdH3FgcH7PLq5d0wUWjV6/ZSVFtOgJCZW1k42saFkHhtu4VJ5QqtuqtGbqTVPIdrMRJENknm4HQNjBRRGlbyBeNF4/cTqzqEaT1pMlrQsS4AWL+/0zb88GzgpBfWgP6DZmi2zjSyMS9nzoyDAff09dGSlVWyRXrVCLkPB9TFLjd+Z3v+ohLmuLV6URgzbsFETvSLEdvRsFSnnY3eL1YK8nw257Sh5RV4BTDZv5Fd1UdFMH8EGgX4Eg4AAiI7rMYVrpW/evGagDSH9qhLAh5q88E7+EGUsTdVw7HoLqDhbUdht8edtl+5x39kHvD32yRv0RY3Y X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Oct 2026 20:21:06.2010 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 9f866ae4-3db0-41a3-8506-08df2255051f X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.118.233];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SN1PEPF000397B3.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS0PR12MB7970 On Sun, Oct 04, 2026 at 02:24:10PM +0100, Will Deacon wrote: > On Sun, Aug 30, 2026 at 04:18:04PM -0700, Nicolin Chen wrote: > > The driver programs and enables the event queue unconditionally, while the > > PRI queue has an ARM_SMMU_FEAT_PRI gating each of its touch points. Yet a > > kdump kernel wants to leave both of the queues alone, which would take an > > is_kdump_kernel() test at every one of those places. > > > > Add an ARM_SMMU_FEAT_EVTQ that the probe always sets, as the event queue is > > architecturally mandatory, and gate the queue's allocation, its interrupt > > and its CR0 and IRQ_CTRL enables on it, so that a later change can turn the > > queue off in a single place. > > > > No functional change intended. > > > > Suggested-by: Jason Gunthorpe > > Suggested-by: Robin Murphy > > Assisted-by: Claude:claude-opus-5 > > Signed-off-by: Nicolin Chen > > --- > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.h | 1 + > > drivers/iommu/arm/arm-smmu-v3/arm-smmu-v3.c | 79 +++++++++++++-------- > > 2 files changed, 52 insertions(+), 28 deletions(-) > > Sashiko has comments about the event queue MSI configuration for this patch. > Please can you have a look? Sashiko raised those because it doesn't read subsequent patches. And I left them as-is because I don't think they worth a change: 1. IRQ_CTRL_EVTQ_IRQEN is never enabled in the kdump mode, so that ARM_SMMU_EVTQ_IRQ_CFG0 line shouldn't matter. 2. arm_smmu_write_msi_msg() is never called in the kdump mode since devm_request_threaded_irq() is guarded with ARM_SMMU_FEAT_EVTQ. Sashiko is only right about the small waste of the MSI vector since it's unused. But, that nvec decrement trick only works for PRIQ, as its MSI index is at top of the list: enum arm_smmu_msi_index { EVTQ_MSI_INDEX, GERROR_MSI_INDEX, PRIQ_MSI_INDEX, ARM_SMMU_MAX_MSIS, // "nvec--" shifts up this, skipping PRIQ }; On the other hand, EVTQ_MSI_INDEX is at 0. Skipping it would need to shift the entire index list; struct arm_smmu_msi_cfg would not work straightforwardly as today. Nicolin