From: Drew Fustini <fustini@kernel.org>
To: Conor Dooley <conor@kernel.org>
Cc: "Adrien Ricciardi" <aricciardi@baylibre.com>,
"Alexandre Ghiti" <alex@ghiti.fr>,
"Albert Ou" <aou@eecs.berkeley.edu>,
"Atish Patra" <atish.patra@linux.dev>,
"Babu Moger" <babu.moger@amd.com>,
"Ben Horgan" <ben.horgan@arm.com>,
"Borislav Petkov" <bp@alien8.de>,
"Chen Pei" <cp0613@linux.alibaba.com>,
"Conor Dooley" <conor.dooley@microchip.com>,
"Conor Dooley" <conor+dt@kernel.org>,
"Dave Hansen" <dave.hansen@linux.intel.com>,
"Dave Martin" <Dave.Martin@arm.com>,
"Fenghua Yu" <fenghuay@nvidia.com>,
"Gong Shuai" <gong.shuai@sanechips.com.cn>,
"Gong Shuai" <gsh517@gmail.com>,
guo.wenjia23@zte.com.cn, "James Morse" <james.morse@arm.com>,
"Kornel Dulęba" <mindal@semihalf.com>,
"Krzysztof Kozlowski" <krzk+dt@kernel.org>,
liu.qingtao2@zte.com.cn,
"Liu Zhiwei" <zhiwei_liu@linux.alibaba.com>,
"Palmer Dabbelt" <palmer@dabbelt.com>,
"Paul Walmsley" <pjw@kernel.org>,
"Peter Newman" <peternewman@google.com>,
"Radim Krčmář" <rkrcmar@ventanamicro.com>,
"Reinette Chatre" <reinette.chatre@intel.com>,
"Rob Herring" <robh@kernel.org>,
"Samuel Holland" <samuel.holland@sifive.com>,
"Sebastian Andrzej Siewior" <bigeasy@linutronix.de>,
"Clark Williams" <clrkwllms@kernel.org>,
"Steven Rostedt" <rostedt@goodmis.org>,
"Tony Luck" <tony.luck@intel.com>,
"Vasudevan Srinivasan" <vasu@rivosinc.com>,
"Ved Shanbhogue" <ved@rivosinc.com>,
"Weiwei Li" <liwei1518@gmail.com>,
"yunhui cui" <cuiyunhui@bytedance.com>,
"Zhanpeng Zhang" <zhangzhanpeng.jasper@bytedance.com>,
linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org,
x86@kernel.org, devicetree@vger.kernel.org,
linux-rt-devel@lists.linux.dev, linux-doc@vger.kernel.org
Subject: Re: [PATCH v9 4/5] dt-bindings: riscv: Add binding for CBQRI controllers
Date: Sun, 4 Oct 2026 22:41:24 -0700 [thread overview]
Message-ID: <asM4hITT4dNVIndy@x1gen8.tail89d63.ts.net> (raw)
In-Reply-To: <20261004-fender-oink-1646de550f3b@spud>
[-- Attachment #1: Type: text/plain, Size: 2995 bytes --]
On Sun, Oct 04, 2026 at 12:05:31AM +0100, Conor Dooley wrote:
> On Sat, Oct 03, 2026 at 12:12:29AM -0700, Drew Fustini wrote:
> > Document the device tree binding for RISC-V CBQRI capacity and bandwidth
> > controllers. Each controller is named by a device-specific compatible
> > followed by the generic compatible. The binding also describes the
> > common riscv,cbqri-rcid and riscv,cbqri-mcid properties, and the
> > optional riscv,cbqri-cache phandle that links a capacity controller to
> > the cache whose capacity it allocates.
> >
> > Assisted-by: LLM
> > Reviewed-by: Conor Dooley <conor.dooley@microchip.com>
> > Co-developed-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Adrien Ricciardi <aricciardi@baylibre.com>
> > Signed-off-by: Drew Fustini <fustini@kernel.org>
> > ---
> > .../devicetree/bindings/riscv/riscv,cbqri.yaml | 97 ++++++++++++++++++++++
> > MAINTAINERS | 1 +
> > 2 files changed, 98 insertions(+)
> >
> > diff --git a/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml
> > new file mode 100644
> > index 000000000000..0924758ebdde
> > --- /dev/null
> > +++ b/Documentation/devicetree/bindings/riscv/riscv,cbqri.yaml
> > @@ -0,0 +1,97 @@
> > +# SPDX-License-Identifier: GPL-2.0-only OR BSD-2-Clause
> > +%YAML 1.2
> > +---
> > +$id: http://devicetree.org/schemas/riscv/riscv,cbqri.yaml#
> > +$schema: http://devicetree.org/meta-schemas/core.yaml#
> > +
> > +title: RISC-V Capacity and Bandwidth QoS Register Interface (CBQRI) controller
> > +
> > +description: |
> > + The RISC-V CBQRI specification defines capacity-controller and
> > + bandwidth-controller register blocks that allocate cache capacity and memory
> > + bandwidth to resource-control IDs (RCIDs) and monitor usage per
> > + monitoring-counter ID (MCID):
> > + https://github.com/riscv-non-isa/riscv-cbqri/blob/main/riscv-cbqri.pdf
> > +
> > + Allocation and monitoring share one register block, and a controller may
> > + implement either or both. A driver discovers which at runtime from the
> > + capabilities register, so the compatible names only the controller type. It
> > + does not distinguish allocation-only, monitoring-only or combined
> > + controllers, and no property declares monitoring support.
> > +
> > +maintainers:
> > + - Drew Fustini <fustini@kernel.org>
> > +
> > +properties:
> > + compatible:
> > + oneOf:
> > + - items:
> > + - enum:
> > + - tenstorrent,ascalon-shared-cache-controller
> > + - const: riscv,cbqri-capacity-controller
> > + - items:
> > + - {}
> > + - const: riscv,cbqri-bandwidth-controller
>
> I think I lead you up the garden path here actually, it needs to be
> "- not: {}", "- {}" permits anything.
Ah, good point. I will change it to "- not: {}" in the next rev.
Thanks,
Drew
[-- Attachment #2: signature.asc --]
[-- Type: application/pgp-signature, Size: 228 bytes --]
next prev parent reply other threads:[~2026-10-05 5:41 UTC|newest]
Thread overview: 10+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-03 7:12 [PATCH v9 0/5] riscv: Add initial CBQRI resctrl support Drew Fustini
2026-10-03 7:12 ` [PATCH v9 1/5] riscv_cbqri: Add capacity controller probe and allocation device ops Drew Fustini
2026-10-03 7:12 ` [PATCH v9 2/5] riscv_cbqri: resctrl: Add cache allocation via capacity block mask Drew Fustini
2026-10-03 7:12 ` [PATCH v9 3/5] riscv_cbqri: Make RESCTRL_FS available on RISC-V Drew Fustini
2026-10-03 7:12 ` [PATCH v9 4/5] dt-bindings: riscv: Add binding for CBQRI controllers Drew Fustini
2026-10-03 7:19 ` sashiko-bot
2026-10-03 7:53 ` Drew Fustini
2026-10-03 23:05 ` Conor Dooley
2026-10-05 5:41 ` Drew Fustini [this message]
2026-10-03 7:12 ` [PATCH v9 5/5] riscv_cbqri: Add CBQRI capacity allocation platform driver Drew Fustini
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=asM4hITT4dNVIndy@x1gen8.tail89d63.ts.net \
--to=fustini@kernel.org \
--cc=Dave.Martin@arm.com \
--cc=alex@ghiti.fr \
--cc=aou@eecs.berkeley.edu \
--cc=aricciardi@baylibre.com \
--cc=atish.patra@linux.dev \
--cc=babu.moger@amd.com \
--cc=ben.horgan@arm.com \
--cc=bigeasy@linutronix.de \
--cc=bp@alien8.de \
--cc=clrkwllms@kernel.org \
--cc=conor+dt@kernel.org \
--cc=conor.dooley@microchip.com \
--cc=conor@kernel.org \
--cc=cp0613@linux.alibaba.com \
--cc=cuiyunhui@bytedance.com \
--cc=dave.hansen@linux.intel.com \
--cc=devicetree@vger.kernel.org \
--cc=fenghuay@nvidia.com \
--cc=gong.shuai@sanechips.com.cn \
--cc=gsh517@gmail.com \
--cc=guo.wenjia23@zte.com.cn \
--cc=james.morse@arm.com \
--cc=krzk+dt@kernel.org \
--cc=linux-doc@vger.kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-riscv@lists.infradead.org \
--cc=linux-rt-devel@lists.linux.dev \
--cc=liu.qingtao2@zte.com.cn \
--cc=liwei1518@gmail.com \
--cc=mindal@semihalf.com \
--cc=palmer@dabbelt.com \
--cc=peternewman@google.com \
--cc=pjw@kernel.org \
--cc=reinette.chatre@intel.com \
--cc=rkrcmar@ventanamicro.com \
--cc=robh@kernel.org \
--cc=rostedt@goodmis.org \
--cc=samuel.holland@sifive.com \
--cc=tony.luck@intel.com \
--cc=vasu@rivosinc.com \
--cc=ved@rivosinc.com \
--cc=x86@kernel.org \
--cc=zhangzhanpeng.jasper@bytedance.com \
--cc=zhiwei_liu@linux.alibaba.com \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®