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Sun, 4 Oct 2026 21:37:51 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Sun, 4 Oct 2026 21:37:49 -0700 Date: Sun, 4 Oct 2026 21:37:48 -0700 From: Nicolin Chen To: Will Deacon CC: , , , , , , , , , , Subject: Re: [PATCH v10 03/13] iommu/arm-smmu-v3: Add ARM_SMMU_FEAT_EVTQ for the event queue Message-ID: References: Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN3PEPF0000B069:EE_|MN0PR12MB6295:EE_ X-MS-Office365-Filtering-Correlation-Id: 86f2abc9-145c-4b64-bd04-08df229a729c X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|23010399003|376014|7416014|82310400026|36860700016|18002099003|22082099003|56012099006|4143699003|10067099003|11063799006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 0OLONGkrCschtZ18UPp67Z8gEvIR6B9vTpauU93HDopdtR19EUilmaUqG4Tz3Uy2S7vFvDkUuG79a/EWFUdOQEcYAAq4SacDaVMx3V7J2weP5C0//yxVhGzZbHluhCE2fY/P8lEzoq4ZDYa9jZhdYufx/XsdB0jJWF+yDzeeumJE/eS4vMOVMxMHPaVo04zLVaykX3F0ely9B5UYUhts87SOj9mlgqF+7sE/0NP1qHbHiUzirmnzT00G7QMY+9EVEpWaJkPNlGhzcs5bu4u6csqYyieHVEPrc2HzaumH+17b+LEYFvZeI/29dP59ceFyzcN6gsIMyFv0YHzcws3Xr0CD7PG7dcPM7CpuIsbpBxdBmPB6tslfUwdzFAzv4BdTLWRCtAMPiPaQwO4kq3K/RS3cjtB8Uz+Z0qL6Jypd3AbU+7n6MfotVaDyIm944JrG X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 04:38:05.1228 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 86f2abc9-145c-4b64-bd04-08df229a729c X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN3PEPF0000B069.namprd21.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: MN0PR12MB6295 On Sun, Oct 04, 2026 at 01:20:52PM -0700, Nicolin Chen wrote: > Sashiko is only right about the small waste of the MSI vector since > it's unused. But, that nvec decrement trick only works for PRIQ, as > its MSI index is at top of the list: > > enum arm_smmu_msi_index { > EVTQ_MSI_INDEX, > GERROR_MSI_INDEX, > PRIQ_MSI_INDEX, > ARM_SMMU_MAX_MSIS, // "nvec--" shifts up this, skipping PRIQ > }; > > On the other hand, EVTQ_MSI_INDEX is at 0. Skipping it would need to > shift the entire index list; struct arm_smmu_msi_cfg would not work > straightforwardly as today. I made a small change swapping those two indexes. Though it cannot break the dependency on the vectors, I think we should be fine as there should be no use case for !FEAT_EVTQ && FEAT_PRI. -----------------------prep patch-------------------------- @@ -59,4 +59,4 @@ static DEFINE_STATIC_KEY_FALSE(arm_smmu_erratum_repeat_tlbi_cfgi_key); enum arm_smmu_msi_index { - EVTQ_MSI_INDEX, GERROR_MSI_INDEX, + EVTQ_MSI_INDEX, PRIQ_MSI_INDEX, @@ -70,7 +70,2 @@ static_assert(sizeof(struct arm_smmu_cd) == NUM_ENTRY_QWORDS * sizeof(u64)); static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { - [EVTQ_MSI_INDEX] = { - ARM_SMMU_EVTQ_IRQ_CFG0, - ARM_SMMU_EVTQ_IRQ_CFG1, - ARM_SMMU_EVTQ_IRQ_CFG2, - }, [GERROR_MSI_INDEX] = { @@ -80,2 +75,7 @@ static phys_addr_t arm_smmu_msi_cfg[ARM_SMMU_MAX_MSIS][3] = { }, + [EVTQ_MSI_INDEX] = { + ARM_SMMU_EVTQ_IRQ_CFG0, + ARM_SMMU_EVTQ_IRQ_CFG1, + ARM_SMMU_EVTQ_IRQ_CFG2, + }, [PRIQ_MSI_INDEX] = { @@ -4967,3 +4967,3 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) - /* Allocate MSIs for evtq, gerror and priq. Ignore cmdq */ + /* Allocate MSIs for gerror, evtq and priq. Ignore cmdq */ ret = platform_device_msi_init_and_alloc_irqs(dev, nvec, arm_smmu_write_msi_msg); @@ -4974,4 +4974,4 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) - smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); smmu->gerr_irq = msi_get_virq(dev, GERROR_MSI_INDEX); + smmu->evtq.q.irq = msi_get_virq(dev, EVTQ_MSI_INDEX); smmu->priq.q.irq = msi_get_virq(dev, PRIQ_MSI_INDEX); ----------------------------------------------------------- -----------------------nvec patch-------------------------- @@ -4952,3 +4961,11 @@ static void arm_smmu_setup_msis(struct arm_smmu_device *smmu) writeq_relaxed(0, smmu->base + ARM_SMMU_GERROR_IRQ_CFG0); - writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); + + /* PRIQ's vector needs EVTQ's to be kept */ + WARN_ON_ONCE(!(smmu->features & ARM_SMMU_FEAT_EVTQ) && + (smmu->features & ARM_SMMU_FEAT_PRI)); + + if (smmu->features & ARM_SMMU_FEAT_EVTQ) + writeq_relaxed(0, smmu->base + ARM_SMMU_EVTQ_IRQ_CFG0); + else + nvec--; ----------------------------------------------------------- I also did a rebase on arm/smmu/updates, resolving merge conflict. I can quickly respin a v11 once we finalize the discussions in the other thread. Thanks Nicolin