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Mon, 5 Oct 2026 01:04:04 -0700 Received: from nvidia.com (10.127.8.10) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Mon, 5 Oct 2026 01:04:03 -0700 Date: Mon, 5 Oct 2026 01:04:00 -0700 From: Nicolin Chen To: Will Deacon CC: Jason Gunthorpe , , , , , , , , , , Subject: Re: [PATCH v10 06/13] iommu/arm-smmu-v3: Add ARM_SMMU_OPT_KDUMP_ADOPT for kdump kernel Message-ID: References: <20261004163501.GB4064@nvidia.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BN2PEPF0000449E:EE_|SJ0PR12MB8138:EE_ X-MS-Office365-Filtering-Correlation-Id: e3797b03-080d-487f-1971-08df22b74693 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|36860700016|82310400026|376014|7416014|23010399003|56012099006|10067099003|4143699003|11063799006|6133799003|22082099003|18002099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: jWXtnhrMv18w7uCYpPbDVe883/Ida1DCb9BIen+GUV5U9A54bh7xp8YsWWDiZ2WhBKBL6PoYfatwQlWdoxIIFPCeHx0w71ZfU+jpQcrrPBw+5Fmg55K5Rsr8ey/N1DpPCWxhLuRAgHx7p3zIrKejvtEm5iVph5gUWUCTYavDJSvn/o4u5C+leL7xqLVmTcn2tUs2ZuZHxCRbW0+VHbHfff0+d3TLfEcL7rALjFtWdq6UrEVb/j2ENrTyepzC+XaYI3IxgkW1jdnzAw5O/5P1o61juTRYYEHoOWIHQfpOivTfNmJQs8qGYKJgV0uHAL7wV1uYVsJya2Bh/my6N2kI6xQMSCLX42AkP/PAWtLaVDHWYYrGb2tfsk++8uOiwrGtc0AcQ5pHE0PzGqeQdQ7FW7CQvexSj+SPEbJWA2QREQIyA26wO7nnzIv7mz5cmvNo X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Oct 2026 08:04:26.6434 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: e3797b03-080d-487f-1971-08df22b74693 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BN2PEPF0000449E.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ0PR12MB8138 On Mon, Oct 05, 2026 at 07:34:25AM +0100, Will Deacon wrote: > On Sun, Oct 04, 2026 at 01:59:04PM -0700, Nicolin Chen wrote: > > On Sun, Oct 04, 2026 at 01:35:01PM -0300, Jason Gunthorpe wrote: > > > On Sun, Oct 04, 2026 at 02:25:07PM +0100, Will Deacon wrote: > > > > > + * - A structural inconsistency at adoption time tosses the entire adoption and > > > > > + * makes the SMMU fall back to a full reset blocking in-flight DMAs. > > > > > + * - L2 stream tables are adopted lazily at master-inserting time, to bound the > > > > > + * peak memory use against a corrupted L1 table; any lazy L2 adoption failure > > > > > + * rejects that device alone, as its blast radius is bounded to the bus. > > > > > + * - Only a coherent SMMU (ARM_SMMU_FEAT_COHERENCY) is supported, as the stream > > > > > + * table adoption is done by memremap with MEMREMAP_WB, which is verified on > > > > > + * the real hardware. Callers of these functions are responsible for gating > > > > > + * ARM_SMMU_FEAT_COHERENCY once during the probe. > > > > > > > > This is an artificial restriction and not one that I'm wild about for kdump: > > > > we should be able to support this for non-coherent SMMUs as well. Is there > > > > anything more to it than using MEMREMAP_WC in that case? > > > > > > I've forgotten why it ended up like this, it was some complication > > > that seemed hard.. MEMREMAP_WC is not the same attribute dma coherent > > > would have used, I'm not sure we have the right stuff to be able to > > > flush any write combining buffer? I'm nervous about that at least. > > > > > > Remember this is not just reading it but it has to operate like this > > > after the fact. In handover you wanted to use the dma cohernent > > > preservation. > > > > > > So, I think this restriction is mostly a lack of the right MEMREMAP > > > flag? It is not insovlable just work outside the scope of this series. > > > > I agree that it's safer to defer that to a followup series. It > > also needs someone who has a non-coherent HW for a full test. > > > > On the other hand, this series is tested by folks from multiple > > organizations, so it's really a needed and verified one. > > I wasn't disputing that, though. I'm saying that it's half finished > without the non-coherent part, so I'd like to understand what's needed > to add that. Can you please explain what is needed beyond using > MEMREMAP_WC? That maps to Normal-NC on arm64, just like the DMA API does. I am not aware of anything beyond MEMREMAP_WC. It should likely need a helper to select flag: ARM_SMMU_FEAT_COHERENCY ? MEMREMAP_WB : MEMREMAP_WC and a verification on a non-coherent SMMU. Thanks Nicolin