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[90.182.211.1]) by smtp.gmail.com with ESMTPSA id 5b1f17b1804b1-4a17f4482c4sm87004535e9.0.2026.10.07.01.07.21 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 01:07:21 -0700 (PDT) Date: Wed, 7 Oct 2026 01:07:20 -0700 From: Charlie Jenkins To: Radim =?utf-8?B?S3LEjW3DocWZ?= Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Samuel Holland , Andy Chiu , Guodong Xu , Zong Li Subject: Re: [PATCH 5/6] riscv: hwprobe: Report XTheadVector only when available Message-ID: References: <20261006075303.205216-1-radim.krcmar@oss.qualcomm.com> <20261006075303.205216-6-radim.krcmar@oss.qualcomm.com> <179133089395.137225.16486951642128892687.b4-review@b4> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: On Wed, Oct 07, 2026 at 09:59:30AM +0200, Radim Krčmář wrote: > 2026-10-06T16:54:53-07:00, Charlie Jenkins : > >> User-mode use of XTheadVector requires non-Off sstatus.VS, which we set > >> only when has_xtheadvector() (CONFIG_RISCV_ISA_XTHEADVECTOR and > >> XTheadVector on all harts). XTheadVector also bundles operations with > >> floating state, which additionally requires non-Off sstatus.FS and hence > >> has_fpu(). hwprobe reports XTheadVector from the per-hart vendor ISA > >> bitmaps alone, so it can advertise an extension that is always disabled > >> in user-mode. > >> > >> Report correct environment to user-mode. > >> > >> Fixes: a5ea53da65c5 ("riscv: hwprobe: Add thead vendor extension probing") > >> Signed-off-by: Radim Krčmář > >> > >> diff --git a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > >> index 2eba34011786..f07aa1c8acac 100644 > >> --- a/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > >> +++ b/arch/riscv/kernel/vendor_extensions/thead_hwprobe.c > >> @@ -1,5 +1,7 @@ > >> // SPDX-License-Identifier: GPL-2.0-only > >> > >> +#include > >> +#include > >> #include > >> #include > >> #include > >> @@ -14,6 +16,7 @@ void hwprobe_isa_vendor_ext_thead_0(struct riscv_hwprobe *pair, const struct cpu > >> { > >> VENDOR_EXTENSION_SUPPORTED(pair, cpus, > >> riscv_isa_vendor_ext_list_thead.per_hart_isa_bitmap, { > >> - VENDOR_EXT_KEY(XTHEADVECTOR); > >> + if (has_xtheadvector() && has_fpu()) > > > > xtheadvector is also gated on FPU=y so this is a reduntant addition. Is > > it worthwhile to make this change? > > With CONFIG_FPU=y, has_fpu() is set to false when a single hart doesn't > have the D, and has_xtheadvector() could still be true. Ahh that's a good point. > > > Is > > it worthwhile to make this change? > > I think that it's sensible to mimic the validation we do for the > non-vendor extension, but users of vendor extensions likely already have > to go out of their way to utilize them, so they can do the sanity checks > too... I can drop the last two patches in v2. I don't know, it seems better to keep standardization if possible and leave the check in here to mimic the standard extensions? - Charlie > > Thanks.