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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1615ece2d14sm9539683c88.1.2026.10.07.04.38.41 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 07 Oct 2026 04:38:44 -0700 (PDT) Date: Wed, 7 Oct 2026 19:38:39 +0800 From: Shawn Guo To: Bjorn Andersson Cc: Stephen Boyd , Brian Masney , Jerome Brunet , Abel Vesa , Bartosz Golaszewski , Taniya Das , Krishna Kurapati , linux-arm-msm@vger.kernel.org, linux-clk@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] clk: qcom: negcc-nord: Keep the AHB2PHY_0 bridge clock always on Message-ID: References: <20261007073146.3162478-1-shengchao.guo@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261007073146.3162478-1-shengchao.guo@oss.qualcomm.com> X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDA3MDA0NiBTYWx0ZWRfX1wcSEKkGZtqK AU78bygsyssN0UDgnzs7Y1WgyTWllXrMvm7kbqsdlPmO88fwTzpjCFF9B3McvyKBjkWWEgjRlpB eORcKzgVmWoYOgiMC5Hxkh0mQP1SJomd75EuAyCtT+tU7X8lyLAfgOL0GYdAjrO4Nwh9tDxCE4q ygLgYfJ8bH70UVr01NQWO3hy7CFt+Hw6Qyx7XMhaPedT95YQ81ODR8TTQok3TzT453iDuim3Bpf vOGiMpzhLFyBQvh/pu6zJd5cOtaGz3R/2GaBaRl8r8KYSpqOA3dPGpTqbRtH0R44Uo/zmgzhSmN Zom1IsNJSemZOlzT+ldA/lWK/M/mHDBfKo39sRXkoQPH9uKoq3NurQqnKnYg6gJjWMqBJu0lje7 RqRou+YIx3J2r8OTdYqP3LL9prkc5PuVsgrBINVXqm0kt+YQKLvo0fuO2vxauRKK1ljjTFtWp6v G7G5cBuLamoofgAoZfA== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDA3MDA0NiBTYWx0ZWRfX+h4XhgNEvo+r orVYDZNcu2czlWglo0zOimBpERyQbR0+48L5O5T7HlvEp4fznyDzTZ8aaI6gP7yN0C2wGrjtJXC pqFAkELNt9bZwk7mDJ2hKWICEdd81zo= X-Proofpoint-ORIG-GUID: v6u8e7HW9u57sewhtEL7AvhNZfkVZHih X-Proofpoint-GUID: v6u8e7HW9u57sewhtEL7AvhNZfkVZHih X-Authority-Analysis: v=2.4 cv=OYkNnRTY c=1 sm=1 tr=0 ts=6ac62f46 cx=c_pps a=SvEPeNj+VMjHSW//kvnxuw==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=rJkE3RaqiGZ5pbrm-msn:22 a=EUspDBNiAAAA:8 a=TEv5oFMQsD92tgmXscwA:9 a=CjuIK1q_8ugA:10 a=Kq8ClHjjuc5pcCNDwlU0:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-07_04,2026-10-06_03,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 lowpriorityscore=0 clxscore=1015 spamscore=0 phishscore=0 bulkscore=0 suspectscore=0 malwarescore=0 priorityscore=1501 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2609040000 definitions=main-2610070046 On Wed, Oct 07, 2026 at 03:31:46PM +0800, Shawn Guo wrote: > NE_GCC_AHB2PHY_CLK gates the AHB2PHY_0 bridge, which fronts the > USB2/USB3-DP PHYs, EUD and PHY_REFGEN_4. It has no consumer in DT, so > clk_disable_unused() gates it before the PHY modules probe. The PHY > initialization sequence then never reaches the PHYs, and DWC3 core soft > reset times out: > > dwc3-qcom a600000.usb: DWC3 controller soft reset failed. > dwc3-qcom a600000.usb: error -ETIMEDOUT: failed to initialize core > > As a result, USB on Nord only works when booting with clk_ignore_unused. > EUD has no clock binding and may be accessed while the USB PHYs are > powered down, so modelling the clock as a PHY consumer is not sufficient. > > Mark the branch as always-on, as is done for the AHB2PHY clocks on > other Qualcomm SoCs (e.g. Kuno, SDX75). > > Assisted-by: LLM > Signed-off-by: Shawn Guo With an offline discussion, it's not desirable to keep AHB2PHY clock always on. Please disregard this patch, and we will try to enable the clock from USB PHY drivers. Shawn > --- > drivers/clk/qcom/negcc-nord.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/clk/qcom/negcc-nord.c b/drivers/clk/qcom/negcc-nord.c > index 68ce4d6278ba..9c9b4a83df1c 100644 > --- a/drivers/clk/qcom/negcc-nord.c > +++ b/drivers/clk/qcom/negcc-nord.c > @@ -812,7 +812,7 @@ static struct clk_branch ne_gcc_ahb2phy_clk = { > .enable_mask = BIT(0), > .hw.init = &(const struct clk_init_data) { > .name = "ne_gcc_ahb2phy_clk", > - .ops = &clk_branch2_ops, > + .ops = &clk_branch2_aon_ops, > }, > }, > }; > -- > 2.43.0 >