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Wed, 14 Oct 2026 20:12:46 +0000 Date: Wed, 14 Oct 2026 16:12:41 -0400 From: Rodrigo Vivi To: Constantinos Chalkias , Bata Roland =?iso-8859-1?Q?Kriszti=E1n?= CC: , , , , , , Subject: Re: [PATCH] drm/xe/hwmon: refresh Battlemage thermal telemetry under force-wake Message-ID: References: <20261012104245.2108030-1-cch@e-psn.eu> Content-Type: text/plain; charset="iso-8859-1" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20261012104245.2108030-1-cch@e-psn.eu> X-ClientProxiedBy: SJ0PR03CA0066.namprd03.prod.outlook.com (2603:10b6:a03:331::11) To CH3PR11MB7180.namprd11.prod.outlook.com (2603:10b6:610:148::5) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH3PR11MB7180:EE_|SJ5PPF56FDAD370:EE_ X-MS-Office365-Filtering-Correlation-Id: 042511c8-e07d-44d5-01fd-08df2a2f8313 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|366016|1800799024|376014|18002099003|22082099003|10067099003|11063799006|261009223027099003|56012099006; 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Fan telemetry can also > become invalid while the physical blower remains elevated. > > Acquire the GT force-wake domain around Battlemage thermal MMIO reads > and allow a short settling interval before reading the register. Route > package, VRAM and VRAM-channel availability reads through the helper. > > Testing showed that an immediate read, as well as a 100-300 us delay, > could leave telemetry stale. A 500-1000 us delay recovered correctly > across repeated inference-to-idle cycles. > > The change is restricted to Battlemage, where the behavior has been > reproduced and validated. > > Signed-off-by: Constantinos Chalkias Cc: Bata Roland Krisztián https://lore.kernel.org/intel-xe/179041811564.526373.13204522833274380927.b70-hwmon-rfc@gmail.com/ I believe you guys are facing the same dificulties and arriving to similar conclusions. If the consensus is that we need this forcewake, let's do it. Let's just avoid duplication of efforts in here. And thank you all for the contributions. > --- > drivers/gpu/drm/xe/xe_hwmon.c | 51 ++++++++++++++++++++++++++++++----- > 1 file changed, 45 insertions(+), 6 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_hwmon.c b/drivers/gpu/drm/xe/xe_hwmon.c > index 5edeac961ec3..fee358ab9a6b 100644 > --- a/drivers/gpu/drm/xe/xe_hwmon.c > +++ b/drivers/gpu/drm/xe/xe_hwmon.c > @@ -3,6 +3,7 @@ > * Copyright © 2023 Intel Corporation > */ > > +#include > #include > #include > #include > @@ -14,6 +15,7 @@ > #include "regs/xe_mchbar_regs.h" > #include "regs/xe_pcode_regs.h" > #include "xe_device.h" > +#include "xe_force_wake.h" > #include "xe_hwmon.h" > #include "xe_mmio.h" > #include "xe_pcode.h" > @@ -946,14 +948,43 @@ static void xe_hwmon_get_voltage(struct xe_hwmon *hwmon, int channel, long *valu > *value = DIV_ROUND_CLOSEST(REG_FIELD_GET(VOLTAGE_MASK, reg_val) * 2500, SF_VOLTAGE); > } > > -static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel) > +static int xe_hwmon_temp_mmio_read(struct xe_hwmon *hwmon, > + struct xe_reg reg, u32 *reg_val) > { > struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); > + > + if (hwmon->xe->info.platform == XE_BATTLEMAGE) { > + struct xe_gt *gt = xe_root_mmio_gt(hwmon->xe); > + > + CLASS(xe_force_wake, fw_ref)(gt_to_fw(gt), XE_FW_GT); > + > + if (!xe_force_wake_ref_has_domain(fw_ref.domains, XE_FW_GT)) > + return -ETIMEDOUT; > + > + /* > + * Allow thermal telemetry to refresh after leaving RC6 > + * before reading the temperature register. > + */ > + usleep_range(500, 1000); > + > + *reg_val = xe_mmio_read32(mmio, reg); > + return 0; > + } > + > + *reg_val = xe_mmio_read32(mmio, reg); > + > + return 0; > +} > + > +static inline bool is_vram_ch_available(struct xe_hwmon *hwmon, int channel) > +{ > int vram_id = channel - CHANNEL_VRAM_N; > struct xe_reg vram_reg; > + u32 reg_val; > > vram_reg = xe_hwmon_get_reg(hwmon, REG_TEMP, channel); > - if (!xe_reg_is_valid(vram_reg) || !xe_mmio_read32(mmio, vram_reg)) > + if (!xe_reg_is_valid(vram_reg) || > + xe_hwmon_temp_mmio_read(hwmon, vram_reg, ®_val) || !reg_val) > return false; > > /* Create label only for available vram channel */ > @@ -1025,15 +1056,19 @@ xe_hwmon_temp_is_visible(struct xe_hwmon *hwmon, u32 attr, int channel) > static int > xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) > { > - struct xe_mmio *mmio = xe_root_tile_mmio(hwmon->xe); > - u64 reg_val; > + u32 reg_val; > + int ret; > > switch (attr) { > case hwmon_temp_input: > switch (channel) { > case CHANNEL_PKG: > case CHANNEL_VRAM: > - reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); > + ret = xe_hwmon_temp_mmio_read(hwmon, > + xe_hwmon_get_reg(hwmon, REG_TEMP, channel), > + ®_val); > + if (ret) > + return ret; > > /* HW register value is in degrees Celsius, convert to millidegrees. */ > *val = REG_FIELD_GET(TEMP_MASK, reg_val) * MILLIDEGREE_PER_DEGREE; > @@ -1043,7 +1078,11 @@ xe_hwmon_temp_read(struct xe_hwmon *hwmon, u32 attr, int channel, long *val) > case CHANNEL_PCIE: > return get_pcie_temp(hwmon, val); > case CHANNEL_VRAM_N...CHANNEL_VRAM_N_MAX: > - reg_val = xe_mmio_read32(mmio, xe_hwmon_get_reg(hwmon, REG_TEMP, channel)); > + ret = xe_hwmon_temp_mmio_read(hwmon, > + xe_hwmon_get_reg(hwmon, REG_TEMP, channel), > + ®_val); > + if (ret) > + return ret; > /* > * This temperature format is 24 bit [31:8] signed integer and 8 bit > * [7:0] fraction. > -- > 2.56.0 >