Re: [PATCH v5] x86/apic: Use EILVT register count from APIC_EFEAT

[Naveen N Rao <naveen@kernel.org>]

[Restore CC list]

I messed up and dropped the Cc list in my reply to Boris, who noticed 
and promptly pointed it out. Restoring the CC list so that the below 
discussion is public.

On Tue, Sep 29, 2026 at 08:13:09PM -0700, Borislav Petkov wrote:
> On Tue, Sep 29, 2026 at 09:49:56PM +0530, Naveen N Rao wrote:
> > No, I think that defeats the purpose of this patch. Part of the 
> > motivation for this patch is that we don't have to care if the EILVT 
> > register count changes again.
> 
> If you really think that for a new CPU, you won't have to touch the kernel,
> then you need to wake up and smell the coffee...
> 
> :-)

One can hope ;)

> 
> > Note that the issue Sashiko is referring to requires three things:
> > - that HW advertise an inflated EILVT Register count in APIC_EFEAT,
> > - that some other _new_ HW unit also advertises an offset > 175 for use 
> >   (the two existing units: IBS and MCE, use a 4-bit field to encode the 
> >   EILVT register number, so those can't trip this)
> > - and, that Linux stay in the old xAPIC mode (rather than x2APIC).
> > 
> > If the first two are true, then that is hardware broken beyond help and 
> > it is hard to imagine Linux additionally being used in xAPIC mode.
> > 
> > This is certainly easier to trigger with virtualization, but there are 
> > far worse ways for the hypervisor to mess with the guest.
> > 
> > So, I don't think this alone is reason enough to clamp the value.
> 
> ... but ok, you feel way stronger about this than me actually cares so sure,
> let's not do anything here. And yes, I kinda agree with some of your points
> too.


Thanks,
Naveen