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Thu, 8 Oct 2026 20:25:27 +0000 Date: Thu, 8 Oct 2026 15:25:23 -0500 From: Frank Li To: "Peng Fan (OSS)" Cc: Linus Walleij , Bartosz Golaszewski , Frank Li , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Shenwei Wang , Andy Shevchenko , linux-gpio@vger.kernel.org, imx@lists.linux.dev, linux-arm-kernel@lists.infradead.org, linux-kernel@vger.kernel.org, Peng Fan Subject: Re: [PATCH v4 09/10] gpio: mxc: introduce MXC_ICR macros and use field_prep/field_get Message-ID: References: <20261007-gpio-mxc-cleanup-v4-0-c9f5a8b50df9@nxp.com> <20261007-gpio-mxc-cleanup-v4-9-c9f5a8b50df9@nxp.com> Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261007-gpio-mxc-cleanup-v4-9-c9f5a8b50df9@nxp.com> X-ClientProxiedBy: AS4PR09CA0027.eurprd09.prod.outlook.com (2603:10a6:20b:5d4::17) To GV2PR04MB11799.eurprd04.prod.outlook.com (2603:10a6:150:2cf::9) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: GV2PR04MB11799:EE_|AS4PR04MB9508:EE_ X-MS-Office365-Filtering-Correlation-Id: 85033b7d-2542-486f-4e96-08df257a49cd X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|366016|1800799024|376014|7416014|19092799006|56012099006|10067099003|11063799006|4143699003|6133799003|22082099003|18002099003; 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The lowercase > variants accept runtime-computed masks. > > This eliminates the intermediate 'bit' variable from both functions and > makes the register access pattern self-documenting. > > No functional change. > > Signed-off-by: Peng Fan > --- > drivers/gpio/gpio-mxc.c | 24 +++++++++++++----------- > 1 file changed, 13 insertions(+), 11 deletions(-) > > diff --git a/drivers/gpio/gpio-mxc.c b/drivers/gpio/gpio-mxc.c > index 9d69524e06db..39de616cd434 100644 > --- a/drivers/gpio/gpio-mxc.c > +++ b/drivers/gpio/gpio-mxc.c > @@ -7,6 +7,7 @@ > // Authors: Daniel Mack, Juergen Beisert. > // Copyright (C) 2004-2010 Freescale Semiconductor, Inc. All Rights Reserved. > > +#include > #include > #include > #include > @@ -174,6 +175,9 @@ static inline bool mxc_gpio_has_power_off(struct mxc_gpio_port *port) > #define GPIO_INT_FALL_EDGE (port->hwdata->fall_edge) > #define GPIO_INT_BOTH_EDGES 0x4 > > +#define MXC_ICR_REG(gpio) (GPIO_ICR1 + (((gpio) & 0x10) >> 2)) > +#define MXC_ICR_MASK(gpio) (0x3U << (((gpio) & 0xf) << 1)) > + > static const struct of_device_id mxc_gpio_dt_ids[] = { > { .compatible = "fsl,imx1-gpio", .data = &imx1_imx21_gpio_hwdata }, > { .compatible = "fsl,imx21-gpio", .data = &imx1_imx21_gpio_hwdata }, > @@ -200,7 +204,7 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > { > struct irq_chip_generic *gc = irq_data_get_irq_chip_data(d); > struct mxc_gpio_port *port = gc->private; > - u32 bit, val; > + u32 val; > u32 gpio_idx = d->hwirq; > int edge; > void __iomem *reg = port->base; > @@ -250,10 +254,9 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > } > > if (edge != GPIO_INT_BOTH_EDGES) { > - reg += GPIO_ICR1 + ((gpio_idx & 0x10) >> 2); /* lower or upper register */ > - bit = gpio_idx & 0xf; > - val = readl(reg) & ~(0x3 << (bit << 1)); > - writel(val | (edge << (bit << 1)), reg); > + reg += MXC_ICR_REG(gpio_idx); > + val = readl(reg) & ~MXC_ICR_MASK(gpio_idx); > + writel(val | field_prep(MXC_ICR_MASK(gpio_idx), edge), reg); look like have not simpify much. can you add help function, such as update_edge(val, gpio_idex, edge). move & ~MXC_ICR_MASK(gpio_idx) and val | field_prep() into it. Frank > } > > writel(1 << gpio_idx, port->base + GPIO_ISR); > @@ -266,16 +269,15 @@ static int gpio_set_irq_type(struct irq_data *d, u32 type) > static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) > { > void __iomem *reg = port->base; > - u32 bit, val; > + u32 val; > int edge; > > guard(gpio_generic_lock_irqsave)(&port->gen_gc); > > - reg += GPIO_ICR1 + ((gpio & 0x10) >> 2); /* lower or upper register */ > - bit = gpio & 0xf; > + reg += MXC_ICR_REG(gpio); > val = readl(reg); > - edge = (val >> (bit << 1)) & 3; > - val &= ~(0x3 << (bit << 1)); > + edge = field_get(MXC_ICR_MASK(gpio), val); > + val &= ~MXC_ICR_MASK(gpio); > if (edge == GPIO_INT_HIGH_LEV) { > edge = GPIO_INT_LOW_LEV; > pr_debug("mxc: switch GPIO %d to low trigger\n", gpio); > @@ -287,7 +289,7 @@ static void mxc_flip_edge(struct mxc_gpio_port *port, u32 gpio) > gpio, edge); > return; > } > - writel(val | (edge << (bit << 1)), reg); > + writel(val | field_prep(MXC_ICR_MASK(gpio), edge), reg); > } > > /* handle 32 interrupts in one status register */ > > -- > 2.51.0 > >