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Thu, 8 Oct 2026 16:43:44 +0000 Date: Thu, 8 Oct 2026 12:43:27 -0400 From: Rodrigo Vivi To: Alexander Usyskin CC: Miquel Raynal , Richard Weinberger , Vignesh Raghavendra , Matthew Brost , Thomas =?iso-8859-1?Q?Hellstr=F6m?= , David Airlie , "Simona Vetter" , , , , , Menachem Adin Subject: Re: [PATCH v3 2/2] drm/xe/nvm: define survivabilty partition Message-ID: References: <20260930-cri_surviv-v3-0-357aeed5fc60@intel.com> <20260930-cri_surviv-v3-2-357aeed5fc60@intel.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20260930-cri_surviv-v3-2-357aeed5fc60@intel.com> X-ClientProxiedBy: SI1PR02CA0059.apcprd02.prod.outlook.com (2603:1096:4:1f5::19) To DS0PR11MB7192.namprd11.prod.outlook.com (2603:10b6:8:13a::22) Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS0PR11MB7192:EE_|DM4PR11MB6336:EE_ X-MS-Office365-Filtering-Correlation-Id: 3517f0ad-c5f0-4c16-88a1-08df255b508e X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|1800799024|366016|23010399003|7416014|376014|56012099006|10067099003|11063799006|4143699003|18002099003|22082099003|3023799007; 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Reviewed-by: Rodrigo Vivi > Define 8M survivability partition for CRI when > storage is open for write override. > > Signed-off-by: Alexander Usyskin > --- > drivers/gpu/drm/xe/xe_nvm.c | 13 ++++++++++--- > 1 file changed, 10 insertions(+), 3 deletions(-) > > diff --git a/drivers/gpu/drm/xe/xe_nvm.c b/drivers/gpu/drm/xe/xe_nvm.c > index 51a1a431ad85..783c3103a8a4 100644 > --- a/drivers/gpu/drm/xe/xe_nvm.c > +++ b/drivers/gpu/drm/xe/xe_nvm.c > @@ -56,10 +56,11 @@ static bool xe_nvm_non_posted_erase(struct xe_device *xe) > } > } > > -static bool xe_nvm_writable_override(struct xe_device *xe) > +static bool xe_nvm_writable_override(struct xe_device *xe, size_t *survivability_size) > { > struct xe_mmio *mmio = xe_root_tile_mmio(xe); > bool writable_override; > + size_t s_size = 0; > struct xe_reg reg; > u32 test_bit, test_val; > > @@ -68,6 +69,7 @@ static bool xe_nvm_writable_override(struct xe_device *xe) > reg = PCODE_SCRATCH(0); > test_bit = FDO_MODE; > test_val = FDO_MODE; > + s_size = SZ_8M; > break; > case XE_BATTLEMAGE: > reg = HECI_FWSTS2(DG2_GSC_HECI2_BASE); > @@ -91,12 +93,17 @@ static bool xe_nvm_writable_override(struct xe_device *xe) > break; > default: > drm_err(&xe->drm, "Unknown platform\n"); > + *survivability_size = 0; > return true; > } > > writable_override = (xe_mmio_read32(mmio, reg) & test_bit) == test_val; > - if (writable_override) > + if (writable_override) { > drm_info(&xe->drm, "NVM access overridden by jumper\n"); > + *survivability_size = s_size; > + } else { > + *survivability_size = 0; > + } > return writable_override; > } > > @@ -143,7 +150,7 @@ int xe_nvm_init(struct xe_device *xe) > if (!nvm) > return -ENOMEM; > > - nvm->writable_override = xe_nvm_writable_override(xe); > + nvm->writable_override = xe_nvm_writable_override(xe, &nvm->survivability_size); > nvm->non_posted_erase = xe_nvm_non_posted_erase(xe); > nvm->bar.parent = &pdev->resource[0]; > nvm->bar.start = GEN12_GUNIT_NVM_BASE + pdev->resource[0].start; > > -- > 2.53.0 >