Re: [PATCH] clocksource/timer-riscv: use riscv_has_extension_likely

From: Jisheng Zhang <jszhang@kernel.org>
To: Daniel Lezcano <daniel.lezcano@kernel.org>,
	Thomas Gleixner <tglx@kernel.org>, Paul Walmsley <pjw@kernel.org>,
	Palmer Dabbelt <palmer@dabbelt.com>,
	Albert Ou <aou@eecs.berkeley.edu>,
	Alexandre Ghiti <alex@ghiti.fr>
Cc: linux-kernel@vger.kernel.org, linux-riscv@lists.infradead.org
Subject: Re: [PATCH] clocksource/timer-riscv: use riscv_has_extension_likely
Date: Fri, 9 Oct 2026 07:57:26 +0800	[thread overview]
Message-ID: <asgt5ngVC6x-L0VO@xhacker> (raw)
In-Reply-To: <20260902040453.6258-1-jszhang@kernel.org>

On Wed, Sep 02, 2026 at 12:04:53PM +0800, Jisheng Zhang wrote:
> Instead of static branch, use riscv_has_extension_likely() to check
> whether SSTC is supported or not. For one thing, this is straight
> forward, no need to add and enable/disable a static branch during
> probe; For another, riscv_has_extension_likely() is based on
> alternative mechanism, it avoid some downsides of static branch, for
> example static branch's metadata in the __jump_table section, which is
> not discarded after ISA extensions are finalized, wastes some space.

Soft ping?

FWICT, this needs riscv arch maintainer review, then clocksource
maintainers can decide to merge it or not.

> 
> Signed-off-by: Jisheng Zhang <jszhang@kernel.org>
> ---
>  drivers/clocksource/timer-riscv.c | 11 ++++-------
>  1 file changed, 4 insertions(+), 7 deletions(-)
> 
> diff --git a/drivers/clocksource/timer-riscv.c b/drivers/clocksource/timer-riscv.c
> index b310e6721fac..151f4f0cfd6c 100644
> --- a/drivers/clocksource/timer-riscv.c
> +++ b/drivers/clocksource/timer-riscv.c
> @@ -29,12 +29,11 @@
>  #include <asm/sbi.h>
>  #include <asm/timex.h>
>  
> -static DEFINE_STATIC_KEY_FALSE(riscv_sstc_available);
>  static bool riscv_timer_cannot_wake_cpu;
>  
>  static void riscv_clock_event_stop(void)
>  {
> -	if (static_branch_likely(&riscv_sstc_available)) {
> +	if (riscv_has_extension_likely(RISCV_ISA_EXT_SSTC)) {
>  		csr_write(CSR_STIMECMP, ULONG_MAX);
>  		if (IS_ENABLED(CONFIG_32BIT))
>  			csr_write(CSR_STIMECMPH, ULONG_MAX);
> @@ -48,7 +47,7 @@ static int riscv_clock_next_event(unsigned long delta,
>  {
>  	u64 next_tval = get_cycles64() + delta;
>  
> -	if (static_branch_likely(&riscv_sstc_available)) {
> +	if (riscv_has_extension_likely(RISCV_ISA_EXT_SSTC)) {
>  #if defined(CONFIG_32BIT)
>  		csr_write(CSR_STIMECMP, ULONG_MAX);
>  		csr_write(CSR_STIMECMPH, next_tval >> 32);
> @@ -112,7 +111,7 @@ static int riscv_timer_starting_cpu(unsigned int cpu)
>  	ce->irq = riscv_clock_event_irq;
>  	if (riscv_timer_cannot_wake_cpu)
>  		ce->features |= CLOCK_EVT_FEAT_C3STOP;
> -	if (static_branch_likely(&riscv_sstc_available))
> +	if (riscv_has_extension_likely(RISCV_ISA_EXT_SSTC))
>  		ce->rating = 450;
>  	clockevents_config_and_register(ce, riscv_timebase, 100, ULONG_MAX);
>  
> @@ -186,10 +185,8 @@ static int __init riscv_timer_init_common(void)
>  		return error;
>  	}
>  
> -	if (riscv_isa_extension_available(NULL, SSTC)) {
> +	if (riscv_isa_extension_available(NULL, SSTC))
>  		pr_info("Timer interrupt in S-mode is available via sstc extension\n");
> -		static_branch_enable(&riscv_sstc_available);
> -	}
>  
>  	error = cpuhp_setup_state(CPUHP_AP_RISCV_TIMER_STARTING,
>  			 "clockevents/riscv/timer:starting",
> -- 
> 2.53.0
> 
> 
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