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a="1564747" X-IronPort-AV: E=Sophos;i="6.27,179,1787036400"; d="scan'208";a="1564747" Received: from fmviesa011.fm.intel.com ([10.60.135.151]) by orvoesa102.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2026 03:40:27 -0700 X-CSE-ConnectionGUID: uynkbYzyQsm+WZ1I78OQRA== X-CSE-MsgGUID: 2U+XNF39ROSidvrT8TCMtA== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,179,1787036400"; d="scan'208";a="6089682" Received: from pgcooper-mobl3.ger.corp.intel.com (HELO localhost) ([10.245.245.93]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 26 Oct 2026 03:40:23 -0700 Date: Mon, 26 Oct 2026 12:40:20 +0200 From: Andy Shevchenko To: Geert Uytterhoeven Cc: Prabhakar , Cosmin Tanislav , Jonathan Cameron , Andy Shevchenko , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: Re: [PATCH v3 8/8] iio: adc: rzt2h: Add support for RZ/V2H(P) SoC Message-ID: References: <20261023175919.160103-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20261023175919.160103-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Mon, Oct 26, 2026 at 11:14:53AM +0100, Geert Uytterhoeven wrote: > On Sat, 24 Oct 2026 at 12:38, Andy Shevchenko > wrote: > > On Fri, Oct 23, 2026 at 06:59:19PM +0100, Prabhakar wrote: ... > > > +static int rzt2h_adc_write_scale(struct iio_dev *indio_dev, > > > + struct iio_chan_spec const *chan, > > > + int val, int val2) > > > +{ > > > + struct rzt2h_adc *adc = iio_priv(indio_dev); > > > + u64 req_scale, scale; > > > + unsigned int i; > > > + > > > + if (!(adc->chip_info->features & RZT2H_ADC_FEATURE_RES_SELECT)) > > > + return -EINVAL; > > > + > > > + req_scale = mul_u32_u32(val, NANO) + val2; > > > > But what's wrong with the simple 1ULL * val * NANO? > > IMO that looks like a useless multiplication, which will be removed > again in some future "cleanup"... > > There is a reason the mul_u32_u32() helper exists... I don't see that. The 9e3d6223d209 ("math64, timers: Fix 32bit mul_u64_u32_shr() and friends") tells a different story. > > > + for (i = 0; i < chan->num_ext_scan_type; i++) { > > > + scale = mul_u32_u32(RZT2H_ADC_VREF_mV, NANO) >> > > > > Similar Q. -- With Best Regards, Andy Shevchenko