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Thu, 15 Oct 2026 12:51:37 -0700 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.9) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.49 via Frontend Transport; Thu, 15 Oct 2026 12:51:35 -0700 Date: Thu, 15 Oct 2026 12:51:33 -0700 From: Nicolin Chen To: Jason Gunthorpe CC: Andrew Jones , , , , , , , , , , , , , , , Subject: Re: [PATCH v6 09/16] iommu/riscv: Reserve an MSI IOVA window for iommufd Message-ID: References: <20260925151659.419512-1-andrew.jones@oss.qualcomm.com> <20260925151659.419512-10-andrew.jones@oss.qualcomm.com> <179209292716.4133959.2758345963634439485.b4-review@b4> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <179209292716.4133959.2758345963634439485.b4-review@b4> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: BL02EPF0002992D:EE_|IA3PR12MB570242:EE_ X-MS-Office365-Filtering-Correlation-Id: c32e24a8-5632-450c-768e-08df2af5c712 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|23010399003|376014|1800799024|7416014|22082099003|10067099003|18002099003|11063799006|260925021911599003|260925022911599003|260925021311599003|4143699003|56012099006; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: ZwXJgfz8qoWHJlNnCCHR6w9D1V92jYNHlSen9HQryYkeNm412nbKRDjgVoZ6DDgIUT5nCnxfLUnyXCOwQUAeSLZfXaxzOjlEfgU339N/b+zgThprxN4xy2bRO4JTEc8bqx3b5ECGro91XbwaEVv71tQYlRNA2/bEiq0hKrUMIa1/n2IyGaEneYWbLZH70zGKZKHJKqw60CCOMKIDh8EMHIDu/5jGfof3H0fHPNla2E7nlu0bMVy1qSlxN/Hkl9vYQ+/HX8cBKtARO5y2HqZZM/VdigmZUV9eO2Dx7X0WeqsmpQCMgRIlNjNPDcMlvva8ZI0Ns3W8vHppkiGYv2a2AYkWWBSoVepvAfGobrTSrbVu6ZifaZLje6U816dDRsczS1/mW6ktjTZWV2MBieng5WbCAIFOoYq990AmzpOLJTbG/meb3PSorx0XbIkFR7bd X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 15 Oct 2026 19:52:00.3278 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: c32e24a8-5632-450c-768e-08df2af5c712 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: BL02EPF0002992D.namprd02.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: IA3PR12MB570242 On Thu, Oct 15, 2026 at 04:35:27PM -0300, Jason Gunthorpe wrote: > > Reserve one page per possible CPU, sufficient for each supervisor IMSIC > > page. Use a 16 MiB base instead of the 128 MiB convention used by ARM > > SMMU. kvmtool places its guest IMSIC at 128 MiB, so with IRQ bypass the > > domain-wide guest MSI address match can also capture host-delivered > > MSI writes to the SW MSI window and misdeliver them to the guest. > > > > 16 MiB falls in a hole in the current kvmtool and QEMU virt memory maps, > > away from their guest IMSIC windows and RAM. Keep the window below > > 4 GiB so devices with 32-bit MSI address registers can use it. > > And this is a good reason you should not follow ARM down this mad > road. Nicolin had some patches to allow userspace to select the SW_MSI > range instead of using a kernel hard coded value, which becomes a > sneaky ABI. It would be much better if riscv starts off on the right > foot instead of continuing this mistake. It was paused due to lack of an immediate interest: https://lore.kernel.org/linux-iommu/cover.1760487869.git.nicolinc@nvidia.com/ If riscv wants it, maybe we can give a push. Nicolin