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Fri, 16 Oct 2026 14:55:10 -0700 (PDT) Date: Fri, 16 Oct 2026 16:55:09 -0500 From: Andy Chiu To: Radim =?iso-8859-1?Q?Krcm=E1r?= Cc: linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, Paul Walmsley , Palmer Dabbelt , Alexandre Ghiti , Samuel Holland , Andy Chiu , Guodong Xu , Zong Li , Charlie Jenkins Subject: Re: [PATCH 6/6] riscv: hwprobe: Report SiFive vector extensions only when available Message-ID: References: <20261006075303.205216-1-radim.krcmar@oss.qualcomm.com> <20261006075303.205216-7-radim.krcmar@oss.qualcomm.com> Precedence: bulk X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Subscribe: List-Unsubscribe: MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20261006075303.205216-7-radim.krcmar@oss.qualcomm.com> On Tue, Oct 06, 2026 at 09:53:03AM +0200, Radim Krcmár wrote: > User-mode use of the SiFive vector extensions requires non-Off > sstatus.VS, which we set only when has_vector() (CONFIG_RISCV_ISA_V and > Zve32x on all harts). Xsfvfnrclipxfqf and Xsfvfwmaccqqq also execute > floating-point instructions, which additionally require non-Off > sstatus.FS and hence has_fpu(). hwprobe reports the extensions from the > per-hart vendor ISA bitmaps alone, so it can advertise extensions that > are always disabled in user-mode. > > Report correct environment to user-mode. > > Fixes: 1a6274f03534 ("riscv: hwprobe: Add SiFive vendor extension support and probe for xsfqmaccdod and xsfqmaccqoq") > Fixes: 1d91224394c9 ("riscv: hwprobe: Add SiFive xsfvfnrclipxfqf vendor extension") > Fixes: d9669e33c8fa ("riscv: hwprobe: Add SiFive xsfvfwmaccqqq vendor extension") > Signed-off-by: Radim Krcmár Reviewed-by: Andy Chiu