From: Ingo Molnar <mingo@kernel.org>
To: Linus Torvalds <torvalds@linux-foundation.org>
Cc: linux-kernel@vger.kernel.org,
Peter Zijlstra <peterz@infradead.org>,
Arnaldo Carvalho de Melo <acme@redhat.com>,
Jiri Olsa <jolsa@kernel.org>,
Alexander Shishkin <alexander.shishkin@linux.intel.com>,
Mark Rutland <mark.rutland@arm.com>,
Namhyung Kim <namhyung@kernel.org>,
linux-perf-users@vger.kernel.org,
Sean Christopherson <seanjc@google.com>
Subject: [GIT PULL] Performance events updates for v7.4
Date: Sun, 18 Oct 2026 12:04:39 +0200 [thread overview]
Message-ID: <atSZt26TkKplm5qA@gmail.com> (raw)
Linus,
Please pull the latest perf/core Git tree from:
git://git.kernel.org/pub/scm/linux/kernel/git/tip/tip.git perf-core-2026-10-18
for you to fetch changes up to f5a78ecccd98a04c47cea1cd63c2a2fdce8a4b48:
Perf events updates:
- Support SIMD/eGPRs/SSP register sampling in perf
(Dapeng Mi, Kan Liang)
- Turn amd_uncore_ctx events into a flexible array (Rosen Penev)
- Finish the work related to fixing the guest PEBS path to not
set unwanted PERF_GLOBAL_CTRL bits, for which urgent fixes
are upstream already (Sean Christopherson)
- Drop redundant counter slot searches in the AMD uncore
driver (Usama Arif)
- Don't WARN when the ext_regs_buf allocation fails (vineash)
- Annotate x86_pmu::hybrid_pmu with __counted_by_ptr (Thorsten Blum)
Thanks,
Ingo
------------------>
Dapeng Mi (20):
perf/x86: Move hybrid PMU initialization before x86_pmu_starting_cpu()
perf/x86/intel: Enable large PEBS sampling for XMMs
perf/x86/intel: Convert x86_perf_regs to per-cpu variables
perf: Eliminate duplicate arch-specific function definitions
perf/x86: Use x86_perf_regs in NMI handlers
x86/fpu: Add update_fpu_state_and_flag() helper
perf/x86/intel: Centralize PERF_PMU_CAP_EXTENDED_REGS updates
perf/x86: Enable XMM register sampling for non-PEBS events
perf/x86: Enable XMM register sampling for REGS_USER case
perf/x86: Support XMM sampling using sample_simd_vec_reg_* fields
perf/x86: Support YMM sampling using sample_simd_vec_reg_* fields
perf/x86: Support ZMM sampling using sample_simd_vec_reg_* fields
perf/x86: Support OPMASK sampling using sample_simd_pred_reg_* fields
perf: Enhance perf_reg_validate() with simd_enabled argument
perf/x86: Support eGPRs sampling using sample_regs_* fields
perf/x86: Support SSP sampling using sample_regs_* fields
perf/x86/intel: Support arch-PEBS based SIMD/eGPRs sampling
perf/x86/intel: Advertise PERF_PMU_CAP_SIMD_REGS capability
perf/x86: Activate back-to-back NMI detection for arch-PEBS induced NMIs
perf/x86/intel: Add sanity check for PEBS record/fragment size
Kan Liang (3):
x86/fpu/xstate: Add xsaves_nmi() helper
perf: Move and enhance has_extended_regs() for arch-specific use
perf: Add sampling support for SIMD registers
Rosen Penev (1):
perf/x86/amd/uncore: Turn amd_uncore_ctx events into a flexible array
Sean Christopherson (6):
perf/x86/intel: Invert names of intel_ctrl_{guest,host}_mask
perf/x86: KVM: Have perf define a dedicated struct for getting guest PEBS data
perf/x86/intel: KVM: Handle cross-mapped PEBS PMCs entirely within KVM
KVM: VMX: Drop a redundant pmu->global_ctrl check when processing pebs_enable
KVM: VMX: Only tell perf to enable PEBS counters for fully enabled PMCs
perf/x86/intel: Check only PMC bits in PEBS_ENABLED when detecting host PEBS usage
Thorsten Blum (1):
perf/x86/intel: Annotate x86_pmu::hybrid_pmu with __counted_by_ptr
Usama Arif (2):
perf/x86/amd/uncore: Remove redundant event slot scan
perf/x86/amd/uncore: Free counter slot by index
vineash (1):
perf/x86: Don't WARN when the ext_regs_buf allocation fails
arch/arm/kernel/perf_regs.c | 8 +-
arch/arm64/kernel/perf_regs.c | 8 +-
arch/csky/kernel/perf_regs.c | 8 +-
arch/loongarch/kernel/perf_regs.c | 8 +-
arch/mips/kernel/perf_regs.c | 8 +-
arch/parisc/kernel/perf_regs.c | 8 +-
arch/powerpc/perf/perf_regs.c | 2 +-
arch/riscv/kernel/perf_regs.c | 8 +-
arch/s390/kernel/perf_regs.c | 2 +-
arch/x86/events/amd/uncore.c | 39 +--
arch/x86/events/core.c | 488 ++++++++++++++++++++++++++++++++--
arch/x86/events/intel/core.c | 154 +++++++----
arch/x86/events/intel/ds.c | 232 ++++++++++++----
arch/x86/events/intel/lbr.c | 2 +-
arch/x86/events/perf_event.h | 217 ++++++++++++++-
arch/x86/include/asm/fpu/sched.h | 5 +-
arch/x86/include/asm/fpu/xstate.h | 3 +
arch/x86/include/asm/kvm_host.h | 9 -
arch/x86/include/asm/msr-index.h | 7 +
arch/x86/include/asm/perf_event.h | 46 +++-
arch/x86/include/uapi/asm/perf_regs.h | 53 ++++
arch/x86/kernel/fpu/core.c | 33 ++-
arch/x86/kernel/fpu/xstate.c | 25 +-
arch/x86/kernel/perf_regs.c | 174 ++++++++++--
arch/x86/kvm/vmx/pmu_intel.c | 28 +-
arch/x86/kvm/vmx/vmx.c | 10 +-
arch/x86/kvm/vmx/vmx.h | 15 +-
arch/x86/xen/pmu.c | 5 +-
include/linux/perf_event.h | 23 ++
include/linux/perf_regs.h | 36 +--
include/uapi/linux/perf_event.h | 49 +++-
kernel/events/core.c | 177 ++++++++++--
32 files changed, 1579 insertions(+), 311 deletions(-)
reply other threads:[~2026-10-18 10:04 UTC|newest]
Thread overview: [no followups] expand[flat|nested] mbox.gz Atom feed
Reply instructions:
You may reply publicly to this message via plain-text email
using any one of the following methods:
* Save the following mbox file, import it into your mail client,
and reply-to-all from there: mbox
Avoid top-posting and favor interleaved quoting:
https://en.wikipedia.org/wiki/Posting_style#Interleaved_style
* Reply using the --to, --cc, and --in-reply-to
switches of git-send-email(1):
git send-email \
--in-reply-to=atSZt26TkKplm5qA@gmail.com \
--to=mingo@kernel.org \
--cc=acme@redhat.com \
--cc=alexander.shishkin@linux.intel.com \
--cc=jolsa@kernel.org \
--cc=linux-kernel@vger.kernel.org \
--cc=linux-perf-users@vger.kernel.org \
--cc=mark.rutland@arm.com \
--cc=namhyung@kernel.org \
--cc=peterz@infradead.org \
--cc=seanjc@google.com \
--cc=torvalds@linux-foundation.org \
/path/to/YOUR_REPLY
https://kernel.org/pub/software/scm/git/docs/git-send-email.html
* If your mail client supports setting the In-Reply-To header
via mailto: links, try the mailto: link
Be sure your reply has a Subject: header at the top and a blank line
before the message body.
This is a public inbox, see mirroring instructions
for how to clone and mirror all data and code used for this inbox
all inboxes | Powered by JetHome®