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Mon, 26 Oct 2026 21:43:13 +0000 (UTC) Received: from az2uksmom4.o.css.fujitsu.com (unknown [10.151.22.204]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2nlsmgm1.o.css.fujitsu.com (Postfix) with ESMTPS id 7387CC00FDD; Mon, 26 Oct 2026 21:43:13 +0000 (UTC) Received: from sm-arm-grace07 (unknown [10.124.178.20]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange ECDHE (P-256) server-signature RSA-PSS (2048 bits) server-digest SHA256) (No client certificate requested) by az2uksmom4.o.css.fujitsu.com (Postfix) with ESMTPS id 36B3A405E32; Mon, 26 Oct 2026 21:43:07 +0000 (UTC) Date: Tue, 27 Oct 2026 06:43:05 +0900 From: Itaru Kitayama To: Marc Zyngier Cc: Paolo Bonzini , Sean Christopherson , Shuah Khan , Oliver Upton , Fuad Tabba , Joey Gouly , Steffen Eiden , Suzuki K Poulose , Zenghui Yu , linux-kernel@vger.kernel.org, kvm@vger.kernel.org, linux-kselftest@vger.kernel.org, linux-arm-kernel@lists.infradead.org, kvmarm@lists.linux.dev Subject: Re: [PATCH v3] KVM: arm64: selftests: Test VNCR translation invalidation Message-ID: References: <20261026-b4-vncr-mapping-test-v3-1-7c094a00d46e@fujitsu.com> <861p9czwxc.wl-maz@kernel.org> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <861p9czwxc.wl-maz@kernel.org> On Mon, Oct 26, 2026 at 08:30:07AM +0000, Marc Zyngier wrote: > On Mon, 26 Oct 2026 03:10:10 +0000, > Itaru Kitayama wrote: > > > > Add a standalone KVM selftest that checks VNCR accesses after L1 > > updates its stage-1 mapping and issues a TLBI. This guards against > > stale VNCR translations, as KVM caches L1's translation of > > VNCR_EL2 and must drop it when L1 invalidates the mapping in > > kvm_handle_s1e2_tlbi(). > > > > Keep VNCR_EL2 unchanged while remapping its backing page A to B then > > again to A. At each step, L2 reads and writes TPIDR_EL2, and L1 > > verifies that the accesses reach the selected page while leaving the > > other page unchanged. > > If you were tracking cross vcpu invalidation and exercising all the > architecture corner cases (such as permission changes and co), that > would be helpful. > > But as it is, it doesn't help much as a validation tool. Its scope is > way too narrow. Thank you for your comments. I will try to incorporate the suggested test scenarios. Thanks, Itaru. > > M. > > -- > Without deviation from the norm, progress is not possible. >