From: Dmitry Ilvokhin <d@ilvokhin.com>
To: Florian Fainelli <f.fainelli@gmail.com>
Cc: linux-mips@vger.kernel.org, manuel.lauss@gmail.com,
Thomas Bogendoerfer <tsbogend@alpha.franken.de>,
Thierry Reding <treding@nvidia.com>,
"Rafael J. Wysocki (Intel)" <rafael@kernel.org>,
Thomas Gleixner <tglx@kernel.org>,
open list <linux-kernel@vger.kernel.org>
Subject: Re: [PATCH] MIPS: Alchemy: Register interrupt chips with the IRQ core
Date: Tue, 20 Oct 2026 12:10:18 +0000 [thread overview]
Message-ID: <atdaKuYVOlnpna2o@shell.ilvokhin.com> (raw)
In-Reply-To: <20261016181602.2152632-1-f.fainelli@gmail.com>
On Fri, Oct 16, 2026 at 11:15:59AM -0700, Florian Fainelli wrote:
> Alchemy initializes its interrupt chips through the set-type callbacks,
> which use irq_set_chip_handler_name_locked() to assign the chip and flow
> handler. This bypasses irq_set_chip() and its descriptor registration.
>
> Since /proc/interrupts switched to iterating the IRQ descriptor maple tree,
> the statically allocated Alchemy descriptors are no longer found. On an
> MTX-1, the file contains only the CPU header and ERR counter even though
> the timer, serial, Ethernet and PCI wireless interrupts work.
>
> Register each IC0/IC1 interrupt chip through irq_set_chip() before setting
> the initial trigger type. Do the same for the Au1300 GPIC. Keep the locked
> set-type callbacks for later trigger changes.
>
> Fixes: 171cc0d9eed1 ("genirq/proc: Speed up /proc/interrupts iteration")
> Signed-off-by: Florian Fainelli <f.fainelli@gmail.com>
Reviewed-by: Dmitry Ilvokhin <d@ilvokhin.com>
prev parent reply other threads:[~2026-10-20 12:10 UTC|newest]
Thread overview: 2+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-16 18:15 Florian Fainelli
2026-10-20 12:10 ` Dmitry Ilvokhin [this message]
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