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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id 5a478bee46e88-367405ed2absm6104926eec.5.2026.10.21.01.42.05 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Wed, 21 Oct 2026 01:42:09 -0700 (PDT) Date: Wed, 21 Oct 2026 14:12:02 +0530 From: Varadarajan Narayanan To: Krzysztof Kozlowski Cc: Ilia Lin , "Rafael J. Wysocki" , Viresh Kumar , Rob Herring , Krzysztof Kozlowski , Conor Dooley , linux-pm@vger.kernel.org, linux-arm-msm@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org Subject: Re: [PATCH] dt-bindings: cpufreq: qcom-nvmem: Allow generic OPP tables Message-ID: References: <20261015-opp-v1-1-f18fb6f9bae1@oss.qualcomm.com> <20261017-calm-tangerine-marmot-2e8bfc@quoll> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="8FUA3P5543VdLmYC" Content-Disposition: inline In-Reply-To: X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDIxMDAzNCBTYWx0ZWRfX5Nj1xsLgLscm v1GXG9ZwdtAnStrEoSHCJFQ/r/E2RFJnaNuZ9JkcBbvwZ7BsT6pCMkrLDR0cNDbuG41xNcg0i+N gOCAjZu1oluLnTkIiJ2WE/v6BrxK2sGYDMjGjFWzPgzSxOzIy0PJut9T/C7ny8XEZGCMXRto5Ca 1vBIDO/lwUi8kjhJFgGCH4jgbIOv1DFicKgU9tnXNdeuRyyl8ZJyRRVnMwHeuvp8aQN88v82oAz PIvQY/+RvRuhrrVLAejBjda+x28nGrd5M1c6ktxaZuAwiUL135LMHhn/a7f4hVqfNkq1cYljOsW 0zMLGoMHZGJMcQ+oHUwaPimQCVVi+Z7ZOUGeyYqcU0zJJhZqVFYuwbW9WNHtzeN2hzDIWszdBC6 yUrmxMlzcv1wyMPCQxiLn4iEUEn5xZ3q+45XZnimGYCJN7DsP+8G/7CkMywyYDmqJzApPE7Hiqs CZ8IZ5wKiec7WWbcklw== X-Proofpoint-ORIG-GUID: dOlUby9NdTyfxRuyScbN-RzHcYF0Iiyq X-Proofpoint-GUID: dOlUby9NdTyfxRuyScbN-RzHcYF0Iiyq X-Proofpoint-Spam-Info: AW1haW4tMjYxMDIxMDAzNCBTYWx0ZWRfX7y0ZGSswUWe6 h9IMRTqPM1KntIJGB+06B9Yu7QHrd44J35hcBFkrHirroZu6/0xHHBFDKyOKXx3orrWfaoQU5v6 DnXrt4ggyV9NjAGn6G1vXOYTwZpzvBs= X-Authority-Analysis: v=2.4 cv=HL5WhYtv c=1 sm=1 tr=0 ts=6ad87ae3 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=_K5XuSEh1TEqbUxoQ0s3:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=iiRzA6RgfTgo7wHqi70A:9 a=CjuIK1q_8ugA:10 a=PvBjEiDu0qDqifS8eEoA:9 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.134,FMLib:17.12.100.49 definitions=2026-10-21_02,2026-10-19_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 impostorscore=0 clxscore=1015 phishscore=0 suspectscore=0 bulkscore=0 malwarescore=0 spamscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610210034 --8FUA3P5543VdLmYC Content-Type: text/plain; charset=us-ascii Content-Disposition: inline On Wed, Oct 21, 2026 at 02:10:10PM +0530, Varadarajan Narayanan wrote: > On Wed, Oct 21, 2026 at 08:17:36AM +0200, Krzysztof Kozlowski wrote: > > On 21/10/2026 07:38, Varadarajan Narayanan wrote: > > > On Sat, Oct 17, 2026 at 06:45:53PM +0200, Krzysztof Kozlowski wrote: > > >> On Thu, Oct 15, 2026 at 04:25:28PM +0530, Varadarajan Narayanan wrote: > > >>> The OPP table node-name pattern also matches peripheral OPP tables on > > >>> supported SoCs. However, it only handles Qualcomm CPU and level OPP > > >>> compatibles, causing unevaluatedProperties errors for generic > > >>> operating-points-v2 tables. > > >> > > >> But the select should not select them. How can I reproduce the issue? > > > > > > Sorry for the delay, it was a long weekend here. > > > > > > With the attached patch, I get the following error. > > > > > Does not apply, > > Sorry. Have rebased to next-20261020 and attached, please see. > > > but exactly that sort of opp-table is already all over the tree. Just > > check yourself. > > From what I see, SoCs that don't use operating-points-v2-kryo-cpu for the > CPU's opp table don't face an issue. Since ipq5210's CPU opp table's > compatible is operating-points-v2-kryo-cpu, it is facing this unevaluated > properties error. > > The qcom-cpufreq-nvmem.yaml change is approved in [1]. And the change to > ipq5210.dtsi is to address the feedback in [2]. > > Thanks > Varada > > 1 - https://lore.kernel.org/linux-arm-msm/20260703-lively-intelligent-raptor-5edfbf@quoll/ > 2 - https://lore.kernel.org/linux-arm-msm/06e6868a-c106-40b1-85fb-5ebbc01eff16@oss.qualcomm.com/ Forgot the attachment... Added now. --8FUA3P5543VdLmYC Content-Type: text/x-diff; charset=us-ascii Content-Disposition: attachment; filename="krzysztof-unevaluated-properties.patch" diff --git a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml index 547265b8b118..2f5dbb59034c 100644 --- a/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml +++ b/Documentation/devicetree/bindings/cpufreq/qcom-cpufreq-nvmem.yaml @@ -27,6 +27,7 @@ select: enum: - qcom,apq8064 - qcom,apq8096 + - qcom,ipq5210 - qcom,ipq5332 - qcom,ipq6018 - qcom,ipq8064 diff --git a/arch/arm64/boot/dts/qcom/ipq5210.dtsi b/arch/arm64/boot/dts/qcom/ipq5210.dtsi index 2cdc10529c48..b8172f6f1030 100644 --- a/arch/arm64/boot/dts/qcom/ipq5210.dtsi +++ b/arch/arm64/boot/dts/qcom/ipq5210.dtsi @@ -84,6 +84,14 @@ memory@80000000 { reg = <0x0 0x80000000 0x0 0x0>; }; + i2c_opp_table_32mhz: opp-table-qup32mhz { + compatible = "operating-points-v2"; + + opp-32000000 { + opp-hz = /bits/ 64 <32000000>; + }; + }; + pmu { compatible = "arm,cortex-a53-pmu"; interrupts = ; @@ -179,6 +187,45 @@ uart1: serial@1a84000 { status = "disabled"; }; + + i2c0: i2c@1a88000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a88000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE2_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c1: i2c@1a8c000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a8c000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE3_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; + + i2c2: i2c@1a94000 { + compatible = "qcom,geni-i2c"; + reg = <0x0 0x01a94000 0x0 0x4000>; + #address-cells = <1>; + #size-cells = <0>; + clocks = <&gcc GCC_QUPV3_WRAP_SE5_CLK>; + clock-names = "se"; + clock-frequency = <400000>; + interrupts = ; + operating-points-v2 = <&i2c_opp_table_32mhz>; + status = "disabled"; + }; }; sdhc: mmc@7804000 { --8FUA3P5543VdLmYC--