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a="1212278" X-IronPort-AV: E=Sophos;i="6.27,170,1787036400"; d="scan'208";a="1212278" Received: from orviesa007.jf.intel.com ([10.64.159.147]) by fmvoesa103.fm.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2026 08:13:41 -0700 X-CSE-ConnectionGUID: n2DUfOjvRROA1dh/XPSPRw== X-CSE-MsgGUID: Iq8tyuFxQVKj66CHfi152g== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,170,1787036400"; d="scan'208";a="3038524" Received: from cpetruta-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.24]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 21 Oct 2026 08:13:38 -0700 Date: Wed, 21 Oct 2026 18:13:36 +0300 From: Andy Shevchenko To: Jonathan Santos Cc: linux-spi@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, linux-iio@vger.kernel.org, linux@analog.com, broonie@kernel.org, robh@kernel.org, krzk+dt@kernel.org, conor+dt@kernel.org, Michael.Hennerich@analog.com, nuno.sa@analog.com, jic23@kernel.org, dlechner@baylibre.com Subject: Re: [PATCH v4 8/9] spi: spi-engine-ex: Add support for multi-CS devices Message-ID: References: <183539c950c013d472c6b46e3f1365b022e7c716.1792435248.git.Jonathan.Santos@analog.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <183539c950c013d472c6b46e3f1365b022e7c716.1792435248.git.Jonathan.Santos@analog.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Tue, Oct 20, 2026 at 10:58:37PM -0300, Jonathan Santos wrote: > The SPI Engine controller only handled the first chip select when > asserting CS lines and configuring CS polarity inversion, ignoring > additional CS indices present in cs_index_mask. > > Update spi_engine_gen_cs() to iterate over all set bits in > cs_index_mask and toggle each corresponding CS line in the assert mask. > Update spi_engine_setup() likewise so that SPI_CS_HIGH polarity is > applied to every active CS index rather than only index 0. > > Set SPI_CONTROLLER_MULTI_CS in the controller flags to reflect the > capability to the SPI core. ... > +static unsigned long spi_engine_get_chipselect_bits(struct spi_device *spi, > + unsigned long index_mask) > +{ > + unsigned long bits = 0; > + unsigned int idx; > + > + for_each_set_bit(idx, &index_mask, SPI_DEVICE_CS_CNT_MAX) > + bits |= BIT(spi_get_chipselect(spi, idx)); > + > + return bits; > +} Since the chipselects are in a sequential range, wouldn't that repeat one of bitmap_gather() / bitmap_scatter()? -- With Best Regards, Andy Shevchenko