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The endpoint > IRQ API uses interrupt numbers in the range 1-N, and existing EPF drivers > already follow that convention. This is defensive validation rather than > a correction to the MSI numbering used by those drivers. > > Signed-off-by: Manikanta Maddireddy > --- Reviewed-by: Frank Li > Changes V1 -> V2: > - Retain only MSI interrupt-number-zero validation from v1 patch 10. > - Rewrite the title and commit message around defensive MSI validation, > and remove the Fixes tag. > > drivers/pci/controller/dwc/pcie-tegra194.c | 2 +- > 1 file changed, 1 insertion(+), 1 deletion(-) > > diff --git a/drivers/pci/controller/dwc/pcie-tegra194.c b/drivers/pci/controller/dwc/pcie-tegra194.c > index 632ecab3c8ea..0f49ea6df8bc 100644 > --- a/drivers/pci/controller/dwc/pcie-tegra194.c > +++ b/drivers/pci/controller/dwc/pcie-tegra194.c > @@ -2026,7 +2026,7 @@ static int tegra_pcie_ep_raise_intx_irq(struct tegra_pcie_dw *pcie, u16 irq) > > static int tegra_pcie_ep_raise_msi_irq(struct tegra_pcie_dw *pcie, u16 irq) > { > - if (unlikely(irq > 32)) > + if (unlikely(!irq || irq > 32)) > return -EINVAL; > > appl_writel(pcie, BIT(irq - 1), APPL_MSI_CTRL_1); > -- > 2.34.1 >