From mboxrd@z Thu Jan 1 00:00:00 1970 Authentication-Results: smtp.subspace.kernel.org; arc=none smtp.remote-ip=194.117.254.33 ARC-Seal: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; cv=none; t=1792668176; b=1euZKYwk43FCqLR/Dj1HV/+c+sEgxTSK7oLvAvMeE3/l7NM7zcKaaErJMH3W7zgynLgS O0X4qfv+2p+pIb0L8K6wtf4XSjhTqRmXqUx9KO3QziP35GLNZodSeJ35rsKObYzkDGElv AtHfdgfQginWcarQPIqZlk+aKcSh1sjxJTsa95A1UdfU0ADjArZrX6MCbeM9bGIOxsx0j MaovGFtenREjvAxfP9haoOhw708bWAdTAd0IVZF1X7MrBZCaQ7x8eCFjXBu88kIJoI3fd VImfdH/XONw3v18qXZpdW0O7bcJEkHcoL8SLTdrGZR+K0EOW+XbmVGIG23AU7rJ4vbQ== ARC-Message-Signature: i=1; d=subspace.kernel.org; s=arc20261015; a=rsa-sha256; c=relaxed/relaxed; t=1792668176; h=DMARC-Filter:DKIM-Signature:Received:Received:X-UD-Smtp-Session:Date: From:To:Cc:Subject:Message-ID:References:MIME-Version:Content-Type: Content-Disposition:In-Reply-To; bh=lIovBDsxm3c+1AuHfs1HngEsYYIn9NYcLWoRryp26/w=; b=YjDdqkuTV6jA81t+9j9lf1e43We2sBKXEi1IF1GVQgTP0IPK17MZQkBLURtFOMgr9Z2y aVmVytTQ5hlv5bgDem5HQJyKj8elKsFH0EPZsMY5P7q0Rz1YQECVgiT0z+B9rXMJPTxTi c40LCXQ/WI7WK7BJifQ5HSFMXuxlrOg+P27pgZJm4NP0NuCOEa/V99mRuH23zOHGoKJfH 2tyt45271aS822xM/Y4KEI7NNzyCxcJzNd3zAJjUmWVg9dk/TfWWnumhTBplTh2W1EGB1 Nw2ZSUr5FSvcs5lbw9lXjmVYRpfcsOziE812Ua8NYnwZVrsPIL44+8UHRjbSqTwJgDg== ARC-Authentication-Results: i=1; smtp.subspace.kernel.org; dmarc=none header.from=sang-engineering.com; spf=pass smtp.mailfrom=sang-engineering.com; arc=none smtp.remote-ip=194.117.254.33 Received: from mail.zeus03.de (zeus03.de [194.117.254.33]) (using TLSv1.3 with cipher TLS_AES_256_GCM_SHA384 (256/256 bits) key-exchange X25519 server-signature ECDSA (prime256v1) server-digest SHA256) (No client certificate requested) by smtp.subspace.kernel.org (Postfix) with ESMTPS id 2CAD7606A31A for ; Thu, 22 Oct 2026 11:22:46 +0000 (UTC) DMARC-Filter: OpenDMARC Filter v1.4.2 smtp.subspace.kernel.org 2CAD7606A31A Authentication-Results: smtp.subspace.kernel.org; dmarc=none (p=none dis=none) header.from=sang-engineering.com Authentication-Results: smtp.subspace.kernel.org; spf=pass smtp.mailfrom=sang-engineering.com DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d= sang-engineering.com; h=date:from:to:cc:subject:message-id :references:mime-version:content-type:in-reply-to; s=k1; bh=lIov BDsxm3c+1AuHfs1HngEsYYIn9NYcLWoRryp26/w=; b=PRRAxsOXcrEuZF1KxMnl bShB1Mhpseyoa1fktDWDt9zMaa+BTseTg6ixm06gGfRM8SC8197/Q9kayDAAU7W7 srwoktpg+lgGcW5TAE+FY5xdRmDt9ydpa1MUZMdYsoBedU38DRZIzFdOIH6c2zh6 1GTu7j4xOpwsMyqGvYXWuFjr/TlwqaOEyMAzFR2+ELVWTYWnYbwLb96F47YF0vFf CLO520wm4nTb9fWzyFvyb5jfmJlhchkubmvLudu0vfhDk7ArWUOpqdHd+cCyWvn/ aT50KZamVh6fR0ps6X9E007mgBy/yfMBB1IzN3gCA30G7z6nEv7KELrSm+7LL/9Q 6g== Received: (qmail 1121144 invoked from network); 22 Oct 2026 13:22:43 +0200 Received: by mail.zeus03.de with ESMTPSA (TLS_AES_256_GCM_SHA384 encrypted, authenticated); 22 Oct 2026 13:22:43 +0200 X-UD-Smtp-Session: l3s3148p1@AWMWFWxeQpkujns/ Date: Thu, 22 Oct 2026 13:22:41 +0200 From: wsa+renesas To: Biju Das Cc: "biju.das.au" , Ulf Hansson , "linux-mmc@vger.kernel.org" , "linux-renesas-soc@vger.kernel.org" , "linux-kernel@vger.kernel.org" , Geert Uytterhoeven , Prabhakar Mahadev Lad Subject: Re: [PATCH v24 11/15] mmc: renesas_sdhi: Add RZ/G3L SDHI support Message-ID: References: <20260820171657.62815-1-biju.das.jz@bp.renesas.com> <20260820171657.62815-12-biju.das.jz@bp.renesas.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: multipart/signed; micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="ysZcyI4lULtAi+wb" Content-Disposition: inline In-Reply-To: --ysZcyI4lULtAi+wb Content-Type: text/plain; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable > > So initially bit 8+9 will have a value. This will be moved to bit 16 > > + 17 first Then we clear the bits 8 + 9. Bit8(SCLKEN) and > > Bit9(SDCLKOFFEN) Okay, I get it now. Thanks for the explanation. > > > Does RZG3L have a dedicated naming? I'd guess *_HWADJ1. I wonder if it > > > makes sense to have a dedicated define for it. I tend to think so. > >=20 > > There is no *_HWADJ1 mentioned in HW manual. > > Hardware manual mention this register as "SDm_SCC_HWADJ2" OK. > >=20 > > > > > > > + if (hwadj2) > > > > + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0x3FFF); > > > > + } else { > > > > sd_scc_write32(host, priv, SH_MOBILE_SDHI_SCC_TMPPORT2, 0x1); > > > > + if (hwadj2) > > > > + sd_scc_write32(host, priv, RZG3L_SDHI_SCC_HWADJ2, 0xFF); > > > > > > Magic values? > >=20 > > HW manual mentions the following, > >=20 > > HWADJ2[15:0] 1FFh Hardware Adjustment. > > For 1.8V operation, specify 00FFh. > > For 3.3V operation, specify 3FFFh. > >=20 > > Is the below macros ok for representing magic values?? > >=20 > > SD_SCC_HWADJ2_1_8V 0xFF > > SD_SCC_HWADJ2_3_3V 0x3FFF If you replace the 'SD_'-prefix with 'RZG3L_SDHI_', then yes :) > > > I wonder how likely it is that a SDHI variant has either only this or > > > only TUNING_DELAY. Do you know of one? What would you think about mer= ging the two? You know the RZ SDHI > > much better... > >=20 > > HWADJ2 present only on RZ/G3L, > > whereas TUNING_DELAY present on both RZ/G2L and RZ/G3L. Ok, no merging then. Was worth asking. One more thing I noticed. I think you can drop 'sdhi_quirks_rzg3l' in favor of 'sdhi_quirks_fixed_addr', or? Good luck hacking the updates. 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