Re: [PATCH] dmaengine: sun6i: use the channel pause enable bit

[Frank Li <Frank.li@oss.nxp.com>]

On Wed, Oct 21, 2026 at 03:02:13PM -0600, James Hilliard wrote:
> The channel pause register uses bit 0 to suspend DMA requests. Bit 1 is
> reserved, but sun6i_dma_pause() writes only that bit and returns success.
> An active peripheral transfer can therefore continue while its client
> expects it to be paused, for example while the 8250 driver reads RX
> residue and copies a partially filled receive buffer.
>
> Use bit 0, as specified by the H616 DMA channel pause register.
> This fixes the pause request itself; it does not add paused-state
> reporting or change the handling of transactions already on the bus.
>
> Fixes: 555859308723 ("dmaengine: sun6i: Add driver for the Allwinner A31 DMA controller")
> Signed-off-by: James Hilliard <james.hilliard1@gmail.com>
> ---

Reviewed-by: Frank Li <Frank.Li@nxp.com>

>  drivers/dma/sun6i-dma.c | 2 +-
>  1 file changed, 1 insertion(+), 1 deletion(-)
>
> diff --git a/drivers/dma/sun6i-dma.c b/drivers/dma/sun6i-dma.c
> index 7704b016aed8..204b0b812431 100644
> --- a/drivers/dma/sun6i-dma.c
> +++ b/drivers/dma/sun6i-dma.c
> @@ -60,7 +60,7 @@
>  #define DMA_CHAN_ENABLE_STOP		0
>
>  #define DMA_CHAN_PAUSE		0x04
> -#define DMA_CHAN_PAUSE_PAUSE		BIT(1)
> +#define DMA_CHAN_PAUSE_PAUSE		BIT(0)
>  #define DMA_CHAN_PAUSE_RESUME		0
>
>  #define DMA_CHAN_LLI_ADDR	0x08
>
> ---
> base-commit: 93f51579e7df248780214094418f205253383cc5
> change-id: 20261021-submit-sun6i-dma-pause-bit-v1-618c1c3877d8
>
> Best regards,
> --
> James Hilliard <james.hilliard1@gmail.com>
>