On Fri, Oct 23, 2026 at 12:03:57PM +0200, Olivier Louvignes wrote:
> DCDC1 (1.5-3.4 V), DCDC2-4 (0.5-1.2 V by 10 mV, then 20 mV steps, DCDC3
> up to 3.4 V by 100 mV), DCDC5 (1.4-3.7 V and 1.2 V), ALDO1-4 and BLDO1-2
> (0.5-3.5 V), DLDO1 (0.5-3.4 V), and DLDO2 and CPUSLDO (0.5-1.4 V by 50
> mV). The DCDC frequency is not known to be configurable.

Acked-by: Mark Brown <broonie@kernel.org>