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a="1592048" X-IronPort-AV: E=Sophos;i="6.27,176,1787036400"; d="scan'208";a="1592048" Received: from orviesa009.jf.intel.com ([10.64.159.149]) by orvoesa109.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2026 03:38:34 -0700 X-CSE-ConnectionGUID: w9T+kWYHQNGD7VXGJP/KAA== X-CSE-MsgGUID: AvxYF/CPSgGNMkzOFLK6fQ== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,176,1787036400"; d="scan'208";a="3854300" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.244.221]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 24 Oct 2026 03:38:30 -0700 Date: Sat, 24 Oct 2026 13:38:27 +0300 From: Andy Shevchenko To: Prabhakar Cc: Cosmin Tanislav , Jonathan Cameron , Andy Shevchenko , David Lechner , Nuno =?iso-8859-1?Q?S=E1?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Philipp Zabel , Geert Uytterhoeven , Magnus Damm , linux-iio@vger.kernel.org, linux-renesas-soc@vger.kernel.org, devicetree@vger.kernel.org, linux-kernel@vger.kernel.org, Prabhakar , Biju Das , Fabrizio Castro , Lad Prabhakar Subject: Re: [PATCH v3 8/8] iio: adc: rzt2h: Add support for RZ/V2H(P) SoC Message-ID: References: <20261023175919.160103-1-prabhakar.mahadev-lad.rj@bp.renesas.com> <20261023175919.160103-9-prabhakar.mahadev-lad.rj@bp.renesas.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261023175919.160103-9-prabhakar.mahadev-lad.rj@bp.renesas.com> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Fri, Oct 23, 2026 at 06:59:19PM +0100, Prabhakar wrote: > Add support for the ADC found on the Renesas RZ/V2H(P) SoC, which shares > the RZ/T2H ADC IP but differs in channel count, sampling, calibration and > resolution support. > > The RZ/V2H(P) ADC provides 8 channels, has a fixed conversion time of > 20 ADCLK cycles, does not support calibration, and supports selectable > 12-bit and 8-bit conversion resolution. > > Expose the fixed sampling frequency as a read-only attribute and allow > the conversion resolution to be changed through the scale attribute. > Use extended scan types so the reported scan type follows the selected > resolution, and prevent resolution changes while buffered capture is > active. ... > +static int rzt2h_adc_write_scale(struct iio_dev *indio_dev, > + struct iio_chan_spec const *chan, > + int val, int val2) > +{ > + struct rzt2h_adc *adc = iio_priv(indio_dev); > + u64 req_scale, scale; > + unsigned int i; > + > + if (!(adc->chip_info->features & RZT2H_ADC_FEATURE_RES_SELECT)) > + return -EINVAL; > + > + req_scale = mul_u32_u32(val, NANO) + val2; But what's wrong with the simple 1ULL * val * NANO? > + for (i = 0; i < chan->num_ext_scan_type; i++) { > + scale = mul_u32_u32(RZT2H_ADC_VREF_mV, NANO) >> Similar Q. > + chan->ext_scan_type[i].realbits; > + if (scale == req_scale) > + break; > + } > + if (i == chan->num_ext_scan_type) > + return -EINVAL; > + > + /* The scan type changes with the resolution. */ > + IIO_DEV_ACQUIRE_DIRECT_MODE(indio_dev, claim); > + if (IIO_DEV_ACQUIRE_FAILED(claim)) > + return -EBUSY; > + > + adc->resolution = i; > + > + return 0; > +} -- With Best Regards, Andy Shevchenko