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Thu, 5 Nov 2026 15:04:59 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Thu, 5 Nov 2026 15:04:55 -0800 Date: Thu, 5 Nov 2026 15:04:52 -0800 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , Subject: Re: [PATCH v9 13/25] iommu/arm-smmu-v3-kvm: Add MMIO emulation Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-14-smostafa@google.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261015200903.2735565-14-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: PH5PEPF0000002B:EE_|LV2PR12MB999096:EE_ X-MS-Office365-Filtering-Correlation-Id: 578f56c2-5365-403d-cac9-08df3b9141bb X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|82310400026|36860700016|23010399003|376014|7416014|1800799024|22082099003|10067099003|18002099003|4143699003|11063799006|56012099006|261009223027099003|261021135927099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: 2mJn4icKzoiLt2T4GtEcX0V8ojcj8D2xg8OOYkV6kEVxNk7mk5n1vCChONov3rjYKQ9p6+ZskSwDdX2Z7ddeakJaFQRvDZxuuqhsp80PY1XaIEXN+DOTaPL2c7bl08dva2A0ouavso+Xqy22icQq+oPrheli2lqaej19wEjyUUv8uYLyut29hhHTFTYZHjaOKt4THDLJOsmBnlxE/3QDzbveaEeC5eYGRbuivywQyHasHpxlj0FlCiJMK+qH+Wf8VizmC5aR2sHYuFpmqm/B8gjTqkwbEtucgETuzJCOHYWASDY/pHfnp99San0CrjeMYzpE9ufQo+o6xrOfTsA1y+yai2ofpE6xc5VsPCWwL8hjHIHEZVQn3xewWQFKEdA2ZmZGVWWWRkZIVSBG3f+GVmxp14RAJZhv6C4/CcstpbbfP3ufdTOHotzw4ZxKbckD X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 23:05:16.8059 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 578f56c2-5365-403d-cac9-08df3b9141bb X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: PH5PEPF0000002B.namprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: LV2PR12MB999096 On Thu, Oct 15, 2026 at 08:08:44PM +0000, Mostafa Saleh wrote: > +static bool smmu_dabt_device(struct hyp_arm_smmu_v3_device *smmu, > + struct user_pt_regs *regs, > + u64 esr, u32 off) > +{ > + bool is_write = esr & ESR_ELx_WNR; > + unsigned int len = BIT((esr & ESR_ELx_SAS) >> ESR_ELx_SAS_SHIFT); > + int rd = (esr & ESR_ELx_SRT_MASK) >> ESR_ELx_SRT_SHIFT; > + const u64 read_write = -1ULL; > + const u64 no_access = 0; > + u64 mask = no_access; > + const u64 read_only = is_write ? no_access : read_write; > + bool is_xzr = (rd == 31); > + u64 val = is_xzr ? 0 : regs->regs[rd]; > + > + switch (off) { > + case ARM_SMMU_IDR0: > + if (len != sizeof(u32)) > + break; Maybe add a small helper to list all 64-bit registers: static unsigned int smmu_reg_width(u32 off) { switch (off) { case ARM_SMMU_CMDQ_BASE: case ARM_SMMU_STRTAB_BASE: case ARM_SMMU_EVTQ_BASE: case ARM_SMMU_PRIQ_BASE: case ARM_SMMU_EVTQ_IRQ_CFG0: case ARM_SMMU_PRIQ_IRQ_CFG0: case ARM_SMMU_GERROR_IRQ_CFG0: return sizeof(u64); default: return sizeof(u32); } } Then it'd be tighter by testing the width once, prior to switch (off)? > + /* Allowed RO 32 bit registers. */ > + case ARM_SMMU_IIDR: > + case ARM_SMMU_IDR5: > + case ARM_SMMU_IDR3: > + case ARM_SMMU_IDR1: > + case ARM_SMMU_IRQ_CTRLACK: > + case ARM_SMMU_GERROR: > + if (len != sizeof(u32)) > + break; > + mask = read_only; > + break; > + } > + > + if (WARN_ON(!mask)) > + goto out_ret; Your cover letter mentions "WARNs are fatal in the hypervisor". Is this WARN_ON fatal? Nicolin