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Thu, 5 Nov 2026 15:15:36 -0800 Received: from nvidia.com (10.127.8.13) by mail.nvidia.com (10.129.68.8) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Thu, 5 Nov 2026 15:15:33 -0800 Date: Thu, 5 Nov 2026 15:15:30 -0800 From: Nicolin Chen To: Bjorn Helgaas CC: Danny Gonzalez , Bjorn Helgaas , David Decotigny , Sheena Mohan , , , Jason Gunthorpe , Pranjal Shrivastava , Joerg Roedel , Lu Baolu , Kevin Tian Subject: Re: [PATCH] PCI/ATS: Disable ATS when ACS TB is set upstream Message-ID: References: <20261020181053.2646782-1-digonzal@google.com> <20261105230412.GA1450377@bhelgaas> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261105230412.GA1450377@bhelgaas> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CY7PEPF000000F1:EE_|CH3PR12MB9196:EE_ X-MS-Office365-Filtering-Correlation-Id: 5c0362b8-143f-4270-6a5d-08df3b92bce9 X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|36860700016|82310400026|1800799024|23010399003|376014|7416014|18002099003|22082099003|10067099003|4143699003|261026140227099003|11063799006|261026121527099003|261028144727099003|261021135927099003|56012099006|261009221227099003|261022105027099003|261022075727099003|261009223027099003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: QAqCTU0rit2IkgxNjRB0q602f8ev+UooF+hdC+SRBoI51eaL3M3lQa9gJthw6cB+2SNL/S4Tz1uWznQlZgJqOy7sC004U2mT+OcD6mp2rsOI8KWV8BngYUfeprxW5mE/VJiQnbH9EjVmKBceBvHmK6xp2qIt29VLk9aNAa5Sxk9bA5+xJ1O2invj0JGL63YvuYR+QCiJqxbw+QFCponO7JXuKSd1ao+FT1KyjW6R0GUZrBAtJjUsU4OZYMQ84yzBTsCg1rtxClEagSz/cflxbRo1R0r/qUo1zDe3yYyFtY74M+Fs6Lpty1fN+IebW1PDfqe+vJBc8CcE+Z60uNR6Ce+vBT/7nhLZ2OjkmW88BSQEzu/l6dCWk9AUuUuksNFOfUqF9lM9EX24rfOUOw7Y6v40LPJj2gQzkNEXDBVQMCWXJzlMlsNtYbUjJzxRxK9z X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 05 Nov 2026 23:15:52.9571 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 5c0362b8-143f-4270-6a5d-08df3b92bce9 X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.161];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: CY7PEPF000000F1.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CH3PR12MB9196 On Thu, Nov 05, 2026 at 05:04:12PM -0600, Bjorn Helgaas wrote: > * pci_dev_reset_iommu_prepare() vs pci_dev_reset_iommu_done() > > Different values will make gdev->reset_depth, group->recovery_cnt, > group->domain, and gdev->blocked get out of sync. > > I think it would be better if _iommu_prepare() and _iommu_done() > themselves tracked what _iommu_done() needs to do, for example > they could do something like this: > > int pci_dev_reset_iommu_prepare(struct pci_dev *pdev, bool *restore) > { > if (!pci_ats_supported(pdev) || !dev_has_iommu(&pdev->dev)) { > *restore = false; > return 0; > } > > *restore = true; > ... > } > > Then pci_dev_reset_iommu_done() wouldn't need to call > pci_ats_supported() or dev_has_iommu(), and users would look like > this: > > int pcie_flr(...) > { > bool restore; > > ret = pci_dev_reset_iommu_prepare(dev, &restore); > ... > if (restore) > pci_dev_reset_iommu_done(dev); > } > > Or I guess we could call pci_dev_reset_iommu_done() > unconditionally and pass it 'restore' and it could test it If the condition here is "an upstream bridge becomes inaccessible during a reset", then the reset/flr itself fails? The patch that you acked yesterday handles such a case: https://lore.kernel.org/linux-iommu/20261105001312.GA1479227@bhelgaas/ Nicolin