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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) by DS7PR12MB6191.namprd12.prod.outlook.com (2603:10b6:8:98::21) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.9; Fri, 6 Nov 2026 11:22:30 +0000 Received: from BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8]) by BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8%5]) with mapi id 15.21.0592.009; Fri, 6 Nov 2026 11:22:29 +0000 Date: Fri, 6 Nov 2026 19:22:25 +0800 From: Richard Cheng To: bhelgaas@google.com, dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, benjamin.cheatham@amd.com Cc: iweiny@kernel.org, ming.li@zohomail.com, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, linux-pci@vger.kernel.org, tglx@kernel.org, wangruikang@iscas.ac.cn, vidyas@nvidia.com, lihaoxiang@isrc.iscas.ac.cn, xiangzao@linux.alibaba.com, shawn.lin@rock-chips.com, alifm@linux.ibm.com, 18255117159@163.com Subject: Re: [PATCH v2 0/2] PCI/CXL: Guard MMIO accesses during reset recovery Message-ID: References: <20261106111829.55823-1-icheng@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?RadfVxTQUw8TEe3+JAsUhRc5HfsqBNdZaSaNDN/QLRAW4sR4Z/3iYPxT6VyD?= =?us-ascii?Q?I5kVd6jcMtEb0WoaXJ3OFHW4faGcm+Fhp6QUjWwfmD33C39paAssPjL3JUEE?= =?us-ascii?Q?M1M+M+UOLaIU9CGcR/FL2mJDXhEaE17hT6GePv4e0SPCBIw0w4dvKlc/xD8T?= =?us-ascii?Q?VRc4J29lEKjMsx0TxCXXWzO6ig48Ga4OyFIFlQKhtP5myXblLedYm/yT90Fn?= =?us-ascii?Q?yAcSv3lzog9RnzliO2z5gMXTFnMSeeimab1ErxQjmK8yT34dDcUKqPZSDopq?= =?us-ascii?Q?D/xuSTx1R/ypi+tEtd48kyzZCZhAoEnwcfzCf1HUBqxsWg4ZmLLbnFKJH/52?= =?us-ascii?Q?dDOHXgcJWyqsiI7DuG1V/w3m8rxccU4TJJXzcRG4ihLqD6byZuCYJFHkMtFx?= =?us-ascii?Q?DAunS2/xbaEltTLZjdgS+PuBfQ263x1HTawlnY/7l5Fseanwvy4SjzqWyOFP?= =?us-ascii?Q?b0yuRQQDct5X607Ao7k42J5Pa9uGptHhelQAUHi9BEDDjUL4x7Z8utkVWnKy?= =?us-ascii?Q?jC/oOKPH3wTdd56gLamIPxjo9+9Eg7c3TkzxAkzsZ/GVy6od8cTyLg/idC/e?= =?us-ascii?Q?FL+YI2MFOmYLxRBb6sC3Dx5frIKra9gr4H64hRYlMB99KhQC4HrKbYS2Z47t?= =?us-ascii?Q?9az2T/nNox1Yoltsj50vgo59E0NnFl29A+Pig645yCG3dt6piVHZq9/S3Zqt?= =?us-ascii?Q?WnRtv67OIqpODlxiKh2fWRWgCyAq/9RWLe03BjZWd8p+h5MPH2TEP0hMHIVr?= =?us-ascii?Q?RMkxpDn7jbZeX2wjatfYoVHd7T21IswJK4+jtfcDXUPaEzQ87xNzxt1lC9WF?= =?us-ascii?Q?lq5M+nF/gl2dwFOuJ9OZBthz1tEi9HlNNbOU/o7xpbnUMFLukXM37UA/85kx?= =?us-ascii?Q?gl/8hY9qXGgbWdff+DXSSdPuQqLiolEa0IihlfQJzmGynekNsTr5GIIsc5nz?= =?us-ascii?Q?0aAUnXea7ecucGEBNehWNV7uCdUjSyex8WquVsRry16NINYmNIuF4tNc1JN+?= =?us-ascii?Q?g7xl6jkWByXxqv6G3VtpgFaMvU2PmIFCTzTtT+whPCsMGLXo4nN1yJqKC4V5?= =?us-ascii?Q?N2DBpCJshNOIehhdzsPf8ii29QD8WR33MD82Jb+uKWTDnk1z87f5JtCkFHLP?= =?us-ascii?Q?qdVEsTJ1UhTOPw8gamaBUioNHJahlLZ66b4KHqOXaYe34yaVHNgzIwSU67f2?= =?us-ascii?Q?SmCfZ6VDEZOcGCM22/Vv04eOfqcplt5cZKhB7vw1zq5OCSLYddn4EaUHM0GC?= =?us-ascii?Q?h1NyJ1aAr7TwO7X5tR4O5dXdruD42gX4Xm9wu1c8/fhpNfaxfG4FRbTJ+FQY?= =?us-ascii?Q?rh0BEKmAdUtfGHp0tqv64uSIiQCw9KRaiAZde3ENudc7Tt8fu7llyDhSUr7O?= =?us-ascii?Q?yMYBwh9M0Oe86M9uI7pzRyw5dki6TvTlO1dKau0Lpn/JBk0UmN2VfXhZIVGT?= =?us-ascii?Q?HNAfYPFmH8F4D5ATX2METD5N6Bah90jrFMZTaTADSz7zuCPzjE2m+szdCb36?= =?us-ascii?Q?8NBy0OlBpWVTLSCzhVxjLDRPmRRvewEtz4XtF6Bzyk/a054/9nZhe3f/ivTr?= =?us-ascii?Q?EAwue0iFsnmqr3K/uDrUdnXiN67CW8HTZ34tZ/4gUUTE31qrS3GAclwrxgEj?= =?us-ascii?Q?mBWY59SBrQ+7b442oAM7K1PBxJ1KHA+CY1oMay2pYYkCUjy2P+Kbx6CBeXaq?= =?us-ascii?Q?LVqtdMil1BBh6TN3FwtAsgp599s5YbQWIAv9lrt2qljGBVRlUoe03JJdun/1?= =?us-ascii?Q?NfZN10j7Lg=3D=3D?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 8ee401df-6960-47ad-214a-08df3bf83e23 X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB2370.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 06 Nov 2026 11:22:29.3937 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: W+vYnHZda3uhPTOpO+QuCLtJYjucd/Nqu698BzBYFzPUQqYIvIPmNvxrL8K+SSg50wYtR/A/K+DT+YKt3muQdA== X-MS-Exchange-Transport-CrossTenantHeadersStamped: DS7PR12MB6191 On Fri, Nov 06, 2026 at 07:18:27PM +0800, Richard Cheng wrote: > PCI reset recovery may proceed with state restoration and driver > reset_done() callbacks even when a device has not recovered. > Accessing device MMIO in that state can cause additional errors, including > DPC containment. > > This series adds checks before two MMIO access paths: MSI-X table > resoration and CXL HDM decoder checking. > > Patch 1 checks the existing PCI Command register read in > __pci_restore_msix_state(). If the read fails or returns all ones, > warn and return before accessing the MSI-X table. > > Patch 2 guards CXL decoder accesses after reset. > The CXL reset_done() callback independently accesses HDM decoder > MMIO to check whether decoder state was lost during reset. > > Changes since v1 [1]: > - Dropped v1 patch 1, since commit e8df1d194c39 > ("PCI: Don't treat ~0 as ready in pci_dev_wait() with RRS SV") > already addresses the issue. > - Dropped v1 patch 2, following Benjamin Cheatham's review. > That some devices rely on the existing fallback behavior. > - Reworked v1 patch 3 into v2 patch 1. Instead of skipping all PCI > state restoration, check config accessibility before MSI-X restoration. > This reduces the impact on other restoration paths. > - Retained v1 patch 4 as v2 patch 2. > > Sorry forgot to attach the link for v1: https://lore.kernel.org/all/20260929020405.9724-1-icheng@nvidia.com/ Best regards, Richard Cheng. > Richard Cheng (2): > PCI/MSI: Skip MSI-X restoration when configuration is inaccessible > cxl/pci: Guard decoder accesses after reset > > drivers/cxl/pci.c | 6 ++++++ > drivers/pci/msi/msi.c | 6 +++++- > 2 files changed, 11 insertions(+), 1 deletion(-) > > > base-commit: f66469d9905b39d2c260a15d7d6db450f4db67c1 > -- > 2.43.0 >