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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id d2e1a72fcca58-8b35921dc8bsm375950b3a.10.2026.11.06.00.08.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 06 Nov 2026 00:09:00 -0800 (PST) Date: Fri, 6 Nov 2026 13:38:50 +0530 From: Vishnu Saini To: Sebastian Andrzej Siewior Cc: Rob Clark , Dmitry Baryshkov , Abhinav Kumar , Jessica Zhang , Sean Paul , Marijn Suijten , David Airlie , Simona Vetter , Clark Williams , Steven Rostedt , Jordan Crouse , Sravanthi Kollukuduru , Archit Taneja , Jeykumar Sankaran , Chandan Uddaraju , Rajesh Yadav , linux-arm-msm@vger.kernel.org, dri-devel@lists.freedesktop.org, freedreno@lists.freedesktop.org, linux-kernel@vger.kernel.org, linux-rt-devel@lists.linux.dev, venkata.valluru@oss.qualcomm.com, Naman S Thaker , stable@vger.kernel.org Subject: Re: [PATCH] drm/msm: split DPU core IRQ handler under CONFIG_PREEMPT_RT Message-ID: References: <20260909-drm-mis-next-split-irq-v1-1-89bc9c512c53@oss.qualcomm.com> <20260910064723.pbZP3vic@linutronix.de> <20260915073614.nvT9zW3S@linutronix.de> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20260915073614.nvT9zW3S@linutronix.de> X-Proofpoint-GUID: ohh8IfkZCByA20A3h7680XMB0hiVbK-a X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTA2MDAzMiBTYWx0ZWRfX4qZQM95Itojk PSkId5QDcU+9UYPtW2Sc25EzFiHUEi7WydUtyWjOSvCVaiseEY0VG8frCu2sDtvugj9M1Rm6Wya OakTCoetgnUm0esAAvBZuLx4NfAhjJf0Wnmf/jFMcbQoqRRdtt+xFJroM3WdnLIZZbu+hAfKse6 nuSGT1rF6zDk8Kum6NOs4Cg+aCJDw7XWtWp8rWK+df24JoPZYb+7Xbj04SU7L87FluG8Js/0BY8 nTC4LE7QfdnFX59rq9qj46fsySbcYWZhFTpRr2RBvT+GLA4wqUwSosrau76YL30LwG4jhwCaZaa /FywVdu3hAfq77foopIvX+M//1PblqrruGUJXTgnF3hbM+M9IQZe+ksz0SqT9BPzP5LqvtxGAGU cSdn+dO7OsEEqeWEbrjUVALTDPb4DfBFKtsqr1E+lCzNCQCjreRNXChiIRQTZtu779JyXeOWN0X EMm+qdGAg3Ku1aF+BRg== X-Proofpoint-ORIG-GUID: ohh8IfkZCByA20A3h7680XMB0hiVbK-a X-Authority-Analysis: v=2.4 cv=X7rHu2Te c=1 sm=1 tr=0 ts=6aed8b1e cx=c_pps a=rEQLjTOiSrHUhVqRoksmgQ==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=kj9zAlcOel0A:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yx91gb_oNiZeI1HMLzn7:22 a=EUspDBNiAAAA:8 a=ZNqZZCZIVyXZx7ky4tIA:9 a=CjuIK1q_8ugA:10 a=2VI0MkxyNR6bbpdq8BZq:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTA2MDAzMiBTYWx0ZWRfXxHYFPMDg3e2a BWAwsuom6Qikb9/jRKVJtKplqJ4G/l4RsZYG6+p01XUQ5NwozAzlLc+r9jwCx5C18XvNHOZBCPm GKwaxrPaNEoVJZlskOyKfRXav1frVDA= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-06_02,2026-11-04_01,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 suspectscore=0 clxscore=1015 impostorscore=0 phishscore=0 malwarescore=0 bulkscore=0 spamscore=0 priorityscore=1501 lowpriorityscore=0 adultscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2611040001 definitions=main-2611060032 On Tue, Sep 15, 2026 at 09:36:14AM +0200, Sebastian Andrzej Siewior wrote: > On 2026-09-11 18:14:04 [+0530], Vishnu Saini wrote: > > On Thu, Sep 10, 2026 at 08:47:23AM +0200, Sebastian Andrzej Siewior wrote: > > > On 2026-09-09 14:22:16 [+0530], vishnu.saini@oss.qualcomm.com wrote: > > > > From: Naman S Thaker > > > > > > > > On a PREEMPT_RT kernel, dpu_core_irq() runs as a true hardirq handler, > > > > > > *why* is this the case. The code you replaces adds some ifdefs around > > > request_irq() with 0 as flags. This does not make it run has hardirq. > > You are right, the statement is incorrect, i will update the commit msg. > > On RT kernel, the dpu_core_irq() runs in threaded context by default. > > This behavior is changed in the commit by calling devm_request_threaded_irq with > > IRQ_ONESHOT flag only for RT kernel using the ifdefs. > > The why would be interesting. Usually things stay threaded to avoid > locking issues down the road. > > The irq is now split into two parts for RT, > > 1: primary handler which does not use sleeping locks, and > > 2: secondary threaded handler which can use sleepable locks. > > For normal kernels, the request_irq() with 0 flag is still used as-is. > > If the split is properly done for RT, the non-RT variant should be able > to use the same without any ifdefs. > > > > > > but it dispatches per-encoder callbacks that take sleepable locks > > > > (spinlock_t becomes an rt_mutex on RT, and some DRM-core locks reached > > > > through vblank/CRC/writeback handling are sleepable as well). Sleeping > > > > inside a hardirq handler is not allowed and eventually crashes the > > > > display, which is what happens after running GLMark2 for a while. > > > > > > That is correct. That is the irq handler are threaded by default and > > > only non-threaded if explicitly requested. > > > > > > I suggest to stick with non-threaded by default. > > > There is only one request_threaded_irq() as far as I can tell and this > > > msm_dp_display_request_irq(): > > > > > > | rc = devm_request_threaded_irq(&pdev->dev, dp->irq, > > > | msm_dp_display_irq_handler, > > > | msm_dp_display_irq_thread, > > > | IRQ_TYPE_LEVEL_HIGH, > > > | "dp_display_isr", dp); > > > > > > and its primary handler will be threaded on PREEMPT_RT, too. So you end > > > up with two threads here. > > You are correct about the primary handler in msm_dp_display_request_irq() being threaded. > > But the request_threaded_irq function in msm_dp_display_request_irq() is not modified in this commit. > > The issue fixed by the current commit relates to msm_mdss_irq crash stack below. > > Why is it the way it is? What is the issue in the stack trace below? > This is not described, is it? Your cleared the top of the report. > Now, msm_dp_display_irq_handler() ors the return value which is wrong. > You can't return IRQ_WAKE_THREAD | IRQ_HANDLED and expect the thread is > woken up. It appears the handler is fires over and over which implies > that something is wrong with your primary handler. > > The way this is requested you supposed to have threaded handler and a > secondary-threaded handler. While msm_dp_display_irq_handler() is > invoked as threaded the IRQ chip masks the interrupt source. If it > returns IRQ_WAKE_THREAD it supposed to mask the interrupt source because > the IRQ-chip unmasks the interrupt while the secondary-threaded handler > is run. It seems this does not work as intended. Thank you for the inputs, we are further debugging this issue. The crash accur because of increased unhandled IRQs on RT kernel, will share update once we have root cause of increased unhandled IRQs. > > [ 152.108462] Call trace: > > [ 152.108465] show_stack+0x18/0x30 (C) > > [ 152.108477] dump_stack_lvl+0x60/0x80 > > [ 152.108484] dump_stack+0x18/0x24 > > [ 152.108489] __report_bad_irq+0x4c/0xec > > [ 152.108496] note_interrupt+0x340/0x394 > > [ 152.108502] handle_irq_event+0x94/0xa0 > > [ 152.108508] handle_level_irq+0xd8/0x16c > > [ 152.108513] handle_irq_desc+0x34/0x5c > > [ 152.108518] generic_handle_domain_irq+0x1c/0x28 > > [ 152.108522] msm_mdss_irq+0x68/0x144 [msm] > > [ 152.108654] handle_irq_desc+0x34/0x5c > > [ 152.108660] generic_handle_domain_irq+0x1c/0x28 > > [ 152.108664] gic_handle_irq+0x4c/0x140 > > [ 152.108669] call_on_irq_stack+0x30/0x48 > > [ 152.108673] do_interrupt_handler+0x80/0x84 > > [ 152.108678] el1_interrupt+0x38/0x58 > > [ 152.108685] el1h_64_irq_handler+0x18/0x24 > > [ 152.108690] el1h_64_irq+0x70/0x74 > > [ 152.108694] __schedule+0x6c/0xc9c (P) > > [ 152.108701] schedule_idle+0x20/0x40 > > [ 152.108705] do_idle+0x17c/0x2c0 > > [ 152.108710] cpu_startup_entry+0x38/0x40 > > [ 152.108714] rest_init+0xd8/0xe0 > > [ 152.108719] console_on_rootfs+0x0/0x6c > > [ 152.108726] __primary_switched+0x88/0x90 > > [ 152.108732] handlers: > > [ 152.108734] [<000000000cabe59c>] irq_default_primary_handler threaded [<00000000779fd542>] msm_irq [msm] > > [ 152.108859] Disabling IRQ #246 > > Sebastian