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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="4dphqbl3ubrnxlyn" Content-Disposition: inline In-Reply-To: --4dphqbl3ubrnxlyn Content-Type: text/plain; protected-headers=v1; charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v6 09/10] dt-bindings: display: tegra: Document 8-bit CPU parallel interface MIME-Version: 1.0 On Fri, Nov 06, 2026 at 04:48:17PM +0200, Svyatoslav Ryhel wrote: > =D0=BF=D1=82, 6 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0=BE 16:= 40 Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5: > > > > On Fri, Nov 06, 2026 at 04:11:12PM +0200, Svyatoslav Ryhel wrote: > > > =D0=BF=D1=82, 6 =D0=BB=D0=B8=D1=81=D1=82. 2026=E2=80=AF=D1=80. =D0=BE= 16:08 Thierry Reding =D0=BF=D0=B8=D1=88=D0=B5: > > > > > > > > On Thu, Nov 05, 2026 at 04:05:09PM +0200, Svyatoslav Ryhel wrote: > > > > > Document 8-bit CPU parallel MIPI DBI Type B interface provided by > > > > > Tegra20/30 SoCs display controller. > > > > > > > > > > Reviewed-by: Rob Herring (Arm) > > > > > Signed-off-by: Svyatoslav Ryhel > > > > > --- > > > > > .../display/tegra/nvidia,tegra20-dbi.yaml | 113 ++++++++++++= ++++++ > > > > > .../display/tegra/nvidia,tegra20-dc.yaml | 22 ++++ > > > > > 2 files changed, 135 insertions(+) > > > > > create mode 100644 Documentation/devicetree/bindings/display/teg= ra/nvidia,tegra20-dbi.yaml > > > > > > > > > [...] > > > > > diff --git a/Documentation/devicetree/bindings/display/tegra/nvid= ia,tegra20-dc.yaml b/Documentation/devicetree/bindings/display/tegra/nvidia= ,tegra20-dc.yaml > > > > > index 69be95afd5627..ffeb124905dbf 100644 > > > > > --- a/Documentation/devicetree/bindings/display/tegra/nvidia,tegr= a20-dc.yaml > > > > > +++ b/Documentation/devicetree/bindings/display/tegra/nvidia,tegr= a20-dc.yaml > > > > > @@ -79,6 +79,16 @@ properties: > > > > > rgb: > > > > > type: object > > > > > > > > > > + "#address-cells": > > > > > + const: 1 > > > > > + > > > > > + "#size-cells": > > > > > + const: 0 > > > > > + > > > > > +patternProperties: > > > > > + "^dbi@[0-1]$": > > > > > + $ref: /schemas/display/tegra/nvidia,tegra20-dbi.yaml# > > > > > > > > I think it might be better to group these under a separate dbi node= at > > > > the top-level, making it a sibling to the "rgb" node. If you add > > > > #address-cells and #size-cells here, I think that means technically= the > > > > "rgb" is now in the same address space as those new dbi nodes and w= ould > > > > need its own "reg" property and such. > > > > > > > > > > Only 1 DBI node per DC is available. Adding address/size cells means > > > nothing for rgb. > > > > If only one node is available, then "reg" isn't the right property. > > "reg" indicates we're somehow addressing the child, which applies to all > > children, so I don't think that would work here. A separate property > > would make more sense in that case. > > >=20 > Check v5 and talk to Mikko I checked v5. I disagree. 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