From: Andy Shevchenko <andriy.shevchenko@linux.intel.com>
To: longzhao@ambarella.com
Cc: Bartosz Golaszewski <brgl@kernel.org>,
linux-gpio@vger.kernel.org, Linus Walleij <linusw@kernel.org>,
Michael Walle <mwalle@kernel.org>, Rob Herring <robh@kernel.org>,
Krzysztof Kozlowski <krzk@kernel.org>,
Krzysztof Kozlowski <krzk+dt@kernel.org>,
Krzysztof Kozlowski <krzysztof.kozlowski@oss.qualcomm.com>,
Conor Dooley <conor+dt@kernel.org>,
devicetree@vger.kernel.org, Long Zhao <zl020895@163.com>,
linux-kernel@vger.kernel.org
Subject: Re: [PATCH v12 09/11] gpio: pl061: switch data path to gpio-regmap
Date: Tue, 27 Oct 2026 10:06:15 +0200 [thread overview]
Message-ID: <auBbdz_fBiKr1tJb@ashevche-desk.local> (raw)
In-Reply-To: <20261027-cv75-gpio-v12-9-c22555400e18@ambarella.com>
On Tue, Oct 27, 2026 at 12:18:56PM +0800, Long Zhao via B4 Relay wrote:
>
> Move get, set and direction onto gpio-regmap. ARM PL061 sets
> GPIO_REGMAP_QUIRK_SET_AFTER_DIR so the output value is written
> after the direction change.
>
> Keep a custom irqchip and irq domain. Create the domain with
> the PL061 private data and let gpio-regmap attach it.
>
> Leave the chained handler's regmap_read() unchecked. mis stays 0
> on failure, so the pending loop does nothing, and
> chained_irq_exit() still runs. irq_type still ignores MMIO write
> returns.
>
> The irqchip uses its own child IRQ lockdep class and clears the
> chained handler only after it was installed, checked with lockdep
> on the CV75 board. irq_set_parent() nests
> the GPIO irq_desc under the AMBA parent for irq_set_wake(). The
> gpiochip IRQ resource helpers cannot be kept here: the gpio_chip is
> not reachable through gpio-regmap's external irq_domain path, so
> GPIOD_FLAG_USED_AS_IRQ is never tracked. This matches the other
> users of that path (gpio-idio-16, gpio-pcie-idio-24,
> gpio-104-idi-48).
Something happened to the text formatting, it's quite unbalanced in terms of
occupied room on each of the lines. Make each of the lines to occupy ~72
characters.
...
> +struct pl061_drvdata {
> + const struct regmap_config *regmap_config;
> + const struct pl061_regs *regs;
> + unsigned int ngpio;
Is here any gap (of 4 bytes) in accordance with `pahole`? If so, you better
relocate 'quirks' somewhere to make int and booleans be together.
> + unsigned long quirks;
> + bool clear_irq_on_type;
> + bool pm;
> + int (*reg_mask_xlate)(struct gpio_regmap *gpio,
> + unsigned int base, unsigned int offset,
> + unsigned int *reg, unsigned int *mask);
> };
...
> +static int pl061_irq_domain_map(struct irq_domain *d, unsigned int virq,
> + irq_hw_number_t hwirq)
> +{
> + struct pl061 *pl061 = d->host_data;
> +
> + irq_set_chip_data(virq, pl061);
> + irq_set_lockdep_class(virq, &pl061_irq_lock_class,
> + &pl061_irq_request_class);
Make it a single line.
> + irq_set_chip_and_handler(virq, &pl061_irq_chip, handle_bad_irq);
> + irq_set_noprobe(virq);
> + irq_set_parent(virq, pl061->parent_irq);
> +
> + return 0;
> +}
...
> static int pl061_probe(struct amba_device *adev, const struct amba_id *id)
> {
> + struct gpio_regmap_config config = {};
> + const struct pl061_drvdata *data;
> struct device *dev = &adev->dev;
> - struct gpio_irq_chip *girq;
> + struct gpio_regmap *gpio_regmap;
> + const struct pl061_regs *regs;
> struct pl061 *pl061;
> void __iomem *base;
> - int ret, irq;
> + int ret;
> + int irq;
Unneeded change.
...
> + if (irq) {
> + irq_set_chained_handler_and_data(irq, pl061_irq_handler, pl061);
> + pl061->irq_handler_installed = true;
Can't we remove the chained handler unconditionally?
> + }
--
With Best Regards,
Andy Shevchenko
next prev parent reply other threads:[~2026-10-27 8:06 UTC|newest]
Thread overview: 18+ messages / expand[flat|nested] mbox.gz Atom feed top
2026-10-27 4:18 [PATCH v12 00/11] gpio: add Ambarella CV75 PL061 support Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 01/11] dt-bindings: gpio: pl061: add Ambarella CV75 variant Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 02/11] gpiolib: regmap: add GPIO_REGMAP_QUIRK_SET_AFTER_DIR Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 03/11] gpio: pl061: drop redundant pending check in the IRQ handler Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 04/11] gpio: pl061: convert register access to regmap Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 05/11] gpio: pl061: use IRQ_TYPE_LEVEL_MASK and IRQ_TYPE_EDGE_BOTH Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 06/11] gpio: pl061: use cleanup helpers for locks Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 07/11] gpio: pl061: keep the parent device in a local Long Zhao via B4 Relay
2026-10-27 7:42 ` Andy Shevchenko
2026-10-27 4:18 ` [PATCH v12 08/11] gpiolib: request ACPI GPIO events for external IRQ domains Long Zhao via B4 Relay
2026-10-27 5:29 ` Mika Westerberg
2026-10-27 4:18 ` [PATCH v12 09/11] gpio: pl061: switch data path to gpio-regmap Long Zhao via B4 Relay
2026-10-27 8:06 ` Andy Shevchenko [this message]
2026-10-27 10:32 ` zl020895
2026-10-27 10:50 ` Andy Shevchenko
2026-10-27 4:18 ` [PATCH v12 10/11] gpio: pl061: add Ambarella register-layout variant Long Zhao via B4 Relay
2026-10-27 4:18 ` [PATCH v12 11/11] gpio: pl061: tidy up IRQ trigger logging Long Zhao via B4 Relay
2026-10-27 8:08 ` Andy Shevchenko
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