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Tue, 27 Oct 2026 06:57:41 -0700 (PDT) Received: from hiagonb ([2804:14c:4c5:8bf0::33ca]) by smtp.gmail.com with ESMTPSA id 71dfb90a1353d-5ec2343a846sm11578284e0c.10.2026.10.27.06.57.31 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 27 Oct 2026 06:57:41 -0700 (PDT) Date: Tue, 27 Oct 2026 10:57:29 -0300 From: Hiago De Franco To: Thomas Bonnefille Cc: Uwe =?utf-8?Q?Kleine-K=C3=B6nig?= , Rob Herring , Krzysztof Kozlowski , Conor Dooley , Chen Wang , Inochi Amaoto , Thomas Petazzoni , =?utf-8?Q?Miqu=C3=A8l?= Raynal , linux-pwm@vger.kernel.org, devicetree@vger.kernel.org, sophgo@lists.linux.dev, linux-kernel@vger.kernel.org, Jingbao Qiu , Krzysztof Kozlowski Subject: Re: [PATCH v8 0/2] riscv: pwm: sophgo: add pwm support for CV1800 Message-ID: References: <20250509-pwm_sophgo-v8-0-cfaebeb8ee17@bootlin.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20250509-pwm_sophgo-v8-0-cfaebeb8ee17@bootlin.com> Hello all, On Fri, May 09, 2025 at 11:45:42AM +0200, Thomas Bonnefille wrote: > The Sophgo CV1800 chip provides a set of four independent > PWM channel outputs. > This series adds PWM controller support for Sophgo cv1800. > > Signed-off-by: Jingbao Qiu > [Thomas since v8] > Signed-off-by: Thomas Bonnefille I see this series is abandoned. I worked on a patch to enable PWM for cv1800b reusing pwm-sophgo-sg2042.c driver [1], as Uwe asked. Is it ok if I take over this patch? If yes, I will wait v7.4-rc1 and send the new series. [1] https://github.com/hiagofranco/linux/tree/v7.3-milkv-duo-pwm > --- > Changes in v8: > - Rewrote supported frequency > - Hardcoded HLPERIOD_BASE and PERIDO_BASE > - Change usage of update_bits to set/clear bits when needed > - Rewrote construct of enablement of PWM > - Fixed OE activation > - Fixed hw state modification in case where pwm value cannot be reached > - Renamed variables > - Errors out for new cases > - Reworded some comments > > v7: https://lore.kernel.org/linux-pwm/20240501083242.773305-1-qiujingbao.dlmu@gmail.com/ > > Changes in v7: > - add detailed Limitations > - using BIT(n) instead BIT(0) << n > - use 0 instead of disable macro > - modify OE judgment criteria > - add devm_regmap_init_mmio error message > - delete unused variable > > v6: https://lore.kernel.org/all/20240406063413.3334639-1-qiujingbao.dlmu@gmail.com/ > > Changes in v6: > - delete the OE function because we plan to use the counter subsystem > instead of capture, so there is no need to reuse this code. > - fix set polarity reverse error. > > v5: https://lore.kernel.org/all/20240314100131.323540-1-qiujingbao.dlmu@gmail.com/ > > Changes in v5: > - drop filename > - fix macro > - optimize cv1800_pwm_set_polarity() > - optimize cv1800_pwm_set_oe() > - add comment for cv1800_pwm_set_oe() > - use ticks replace tem > - fix duty_cycle larger than period_val > - use devm_clk_rate_exclusive_get() replace > clk_rate_exclusive_get() > - map linux polarity to register polarity > > v4: https://lore.kernel.org/all/20240304085933.1246964-1-qiujingbao.dlmu@gmail.com/ > > datasheet Link: https://github.com/milkv-duo/duo-files/blob/main/duo/datasheet/CV1800B-CV1801B-Preliminary-Datasheet-full-en.pdf > page 614 > > Changes in v4: > - use macro instead of npwm number > - add support for polarity feature > - add support for Output-Enable/OE feature > > v3: https://lore.kernel.org/all/20240223082014.109385-1-qiujingbao.dlmu@gmail.com/ > > Changes in v3: > - use 0x08 instead of macro > - split if statements based on conditions > - in order to round up, first calculate the > number of high-level cycles, then subtract > it from the PERIOD to obtain the number of HLPERIOD > - use new pwmchip_alloc() API instead of old style > > v2: https://lore.kernel.org/all/20240212121729.1086718-1-qiujingbao.dlmu@gmail.com/ > > Changes in v2: > - drop full stop from subject > - re-order maintainers and description > - pass checkpatch.pl --strict > - fix naming errors > - add "Limitations" section > - use a driver specific prefix for all defines > - using bool instead u32 in cv1800_pwm_enable > - check and set state->polarity > - use mul_u64_u64_div_u64 > - use clk_rate_exclusive_get(), balance with clk_rate_exclusive_put() > - using macro definitions instead of shift operations > - remove shift operation on 0 > - use priv replace cv_pwm > - hardcode npwm > - set atomic to true > - remove MODULE_ALIAS > > v1: https://lore.kernel.org/all/20240207055856.672184-1-qiujingbao.dlmu@gmail.com/ > > --- > Jingbao Qiu (2): > dt-bindings: pwm: sophgo: add pwm for Sophgo CV1800 series SoC > pwm: sophgo: add pwm support for Sophgo CV1800 SoC > > .../devicetree/bindings/pwm/sophgo,cv1800-pwm.yaml | 45 ++++ > drivers/pwm/Kconfig | 10 + > drivers/pwm/Makefile | 1 + > drivers/pwm/pwm-cv1800.c | 294 +++++++++++++++++++++ > 4 files changed, 350 insertions(+) > --- > base-commit: 0af2f6be1b4281385b618cb86ad946eded089ac8 > change-id: 20250407-pwm_sophgo-5032b3858c27 > > Best regards, > -- > Thomas Bonnefille > Best regards, -- Hiago