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a="1818596" X-IronPort-AV: E=Sophos;i="6.27,181,1787036400"; d="scan'208";a="1818596" Received: from fmviesa012.fm.intel.com ([10.60.135.152]) by orvoesa107.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2026 08:38:27 -0700 X-CSE-ConnectionGUID: xN9ZqAOeTEuRkzWbDeg+qw== X-CSE-MsgGUID: gEq44FMGTVKwxPK166bx4Q== X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="6.27,181,1787036400"; d="scan'208";a="6330552" Received: from klitkey1-mobl1.ger.corp.intel.com (HELO localhost) ([10.245.245.196]) by smtpauth.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 27 Oct 2026 08:38:18 -0700 Date: Tue, 27 Oct 2026 17:38:15 +0200 From: Andy Shevchenko To: Greg Kroah-Hartman Cc: Jiri Slaby , Joshua Rogers , Chris Mason , Josef Bacik , Tony Lindgren , Rafael Gago Castano , Florian Fainelli , Ilpo =?iso-8859-1?Q?J=E4rvinen?= , Peter Hurley , Heikki Krogerus , Crescent Hsieh , Frank Li , Sherry Sun , Sascha Hauer , Pengutronix Kernel Team , Fabio Estevam , Manivannan Sadhasivam , Olof Johansson , Andreas =?iso-8859-1?Q?F=E4rber?= , Arnd Bergmann , Krzysztof Kozlowski , Peter Griffin , Alim Akhtar , Robert Baldyga , Thomas Abraham , Kukjin Kim , Patrice Chotard , Srinivas Kandagatla , Maxime Coquelin , Alexandre Torgue , Andy Shevchenko , Vladimir Zapolskiy , Al Cooper , linux-kernel@vger.kernel.org, linux-serial@vger.kernel.org, Bjorn Helgaas , Uwe =?iso-8859-1?Q?Kleine-K=F6nig_=28The_Capable_Hub=29?= , Danilo Krummrich , stable Subject: Re: [PATCH 13/24] serial: 8250: dfl: validate MMIO resource size and regshift Message-ID: References: <20261027-tty-llm-v1-0-99b0202ae546@linuxfoundation.org> <20261027-tty-llm-v1-13-99b0202ae546@linuxfoundation.org> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261027-tty-llm-v1-13-99b0202ae546@linuxfoundation.org> Organization: Intel Finland Oy - BIC 0357606-4 - c/o Alberga Business Park, 6 krs, Bertel Jungin Aukio 5, 02600 Espoo On Tue, Oct 27, 2026 at 12:06:39PM +0100, Greg Kroah-Hartman wrote: > The driver passes the DFL feature's raw MMIO resource to the 8250 core > without verifying that the resource covers the full UART register > window. Add a regshift sanity check and validate that the MMIO resource > is large enough for 8250 register accesses up to register 7 at the > configured register spacing and access width. Same comment as per previous patch. Take the bar size, take all data from FPGA, validate against given limits. -- With Best Regards, Andy Shevchenko