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Tue, 27 Oct 2026 17:41:02 +0000 Date: Tue, 27 Oct 2026 10:41:00 -0700 From: "Luck, Tony" To: Reinette Chatre CC: Fenghua Yu , Maciej Wieczor-Retman , Peter Newman , James Morse , Babu Moger , "Drew Fustini" , Dave Martin , Chen Yu , , , Subject: Re: [RFC PATCH 0/8] arm,x86,fs/resctrl: Support asymmetric L2 cache allocation Message-ID: References: <20261026215718.16810-1-tony.luck@intel.com> <106caf0a-8644-4801-9591-80be38b39418@intel.com> Content-Type: text/plain; charset="utf-8" Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <106caf0a-8644-4801-9591-80be38b39418@intel.com> X-ClientProxiedBy: SJ0PR03CA0228.namprd03.prod.outlook.com (2603:10b6:a03:39f::23) To CH8PR11MB403433.namprd11.prod.outlook.com (2603:10b6:610:32f::10) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: CH8PR11MB403433:EE_|PH0PR11MB4933:EE_ X-MS-Office365-Filtering-Correlation-Id: 81ed2572-5713-4127-5505-08df3451785b X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|366016|261026121527099003|56012099006|4143699003|261021121427099003|261009223027099003|261022075727099003|261022105027099003|10067099003|11063799006|18002099003|22082099003|6133799003|3023799007|261026140227099003; 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N.B. it is assumned > > that the only point of asymmetry is the cache bit mask length. Other > > parameters must be the same (but code doesn't check). > > > > Overall approach is to add the per-L2 cache bitmask length to the domain > > and use that everywhere instead of using a single value from the control. > > > > Patch 1 changes the format of the per-control "max" file and should be > > merged back into Reinette's multi-control series so this file can have > > a consistent format from first upstream introduction. > > > > Patches 2-5 are enumeration and preperation. > > > > Patch 6 introduces, initializes, and uses the per-domain cache bit mask > > length field (arm/MPAM change needs careful scrutiny). > > > > Patch 7 enables asymmetric L2 for x86 CPUs that enumerate it. N.B. it > > renammes the resource from "L2" to "L2A" to avoid user interface issues > > with tools that expect L2 cache allocation to be symmetric. > > I did a quick scan and it seems to ignore the the distinction between a resource > and control as highlighted the previous time you brought up this work. Specifically, > please see: > > https://lore.kernel.org/lkml/eaeb4259-46d6-4656-8354-669ad32654b5@intel.com/ I think I see now. You want the "asymmetry" to be a property of the control, not of the resource. So the resource name stays as "L2" but the control gets a suffix (e.g. "_ASYM") File system looks like this: # tree . ├── cpus ├── cpus_list ├── info │   ├── L2 │   │   ├── bit_usage │   │   ├── control_mode │   │   ├── min_cbm_bits │   │   ├── num_closids │   │   ├── schemata │   │   │   └── L2_ASYM │   │   │   ├── max │   │   │   ├── min_bits │   │   │   └── type │   │   ├── shareable_bits │   │   └── sparse_masks │   └── last_cmd_status ├── mode ├── schemata ├── size └── tasks and the schemata file: # cat schemata L2_ASYM:0=fff;1=fff;2=fff;3=fff;4=ffff;5=ffff;8=ffff > > Also, why does patch #1 drop the 0x prefix from new control interface when displaying hex > values to user space? This is a significant change for which patch #1 does not provide > a motivation. Sorry for missing out the justification. I thought that matching the format of the schemata file would be more useful. Then someone could reset a group to maximum values with: # echo L2_ASYM:$(cat /sys/fs/resctrl/info/L2/schemata/L2_ASYM/max) > schemata But if you like the "0x" prefixes I'm OK with that too. Just need to replace "cat" with "sed -e s/0x//g" to reset to maximum values. > > Reinette -Tony