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[103.229.18.19]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1a75a5594efsm19594399c88.2.2026.10.29.04.49.30 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 29 Oct 2026 04:49:38 -0700 (PDT) Date: Thu, 29 Oct 2026 17:19:27 +0530 From: Himanshu Chauhan To: Zhanpeng Zhang Cc: Paul Walmsley , Palmer Dabbelt , Albert Ou , Alexandre Ghiti , Conor Dooley , Anup Patel , =?iso-8859-1?Q?Cl=E9ment_L=E9ger?= , Yunhui Cui , Atish Patra , Peter Zijlstra , Ingo Molnar , Arnaldo Carvalho de Melo , Namhyung Kim , Mark Rutland , Alexander Shishkin , Jiri Olsa , Ian Rogers , Adrian Hunter , James Clark , Will Deacon , Thomas Gleixner , Jonathan Corbet , Randy Dunlap , Shuah Khan , yuanzhu@bytedance.com, yang.yicong@picoheart.com, yang.susheng@zte.com.cn, linux-riscv@lists.infradead.org, linux-kernel@vger.kernel.org, linux-perf-users@vger.kernel.org, linux-doc@vger.kernel.org, linux-kselftest@vger.kernel.org Subject: Re: [PATCH v12 03/11] riscv: sse: mask events during shutdown and kexec Message-ID: References: <20261029074853.35467-1-zhangzhanpeng.jasper@bytedance.com> <20261029074853.35467-4-zhangzhanpeng.jasper@bytedance.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <20261029074853.35467-4-zhangzhanpeng.jasper@bytedance.com> X-Authority-Analysis: v=2.4 cv=X4nHu2Te c=1 sm=1 tr=0 ts=6ae332d5 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=Ou0eQOY4+eZoSc0qltEV5Q==:17 a=kj9zAlcOel0A:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=3WHJM1ZQz_JShphwDgj5:22 a=VwQbUJbxAAAA:8 a=EUspDBNiAAAA:8 a=968KyxNXAAAA:8 a=d9ZL6iGcv7SM8b05mYgA:9 a=CjuIK1q_8ugA:10 a=O8hF6Hzn-FEA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-GUID: pwvfw_LudOznBo6FSq6-uTftid1SlWaB X-Proofpoint-ORIG-GUID: pwvfw_LudOznBo6FSq6-uTftid1SlWaB X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDI5MDA0NSBTYWx0ZWRfX7O06VaoSN15R xf9XU5M4/yNJUJofdJkxEXhqHqc4BuhnMMP3ehzw2jY4UZY2iY7dr5ouAYmvoikQWOnSZvzoG90 9SmkEQFp4mLVwk9zfssPaLn/oyN6Vt0OucuLIq10By54fHZcYeVRVfRMa/e+ZwR99BSQvEdptdH f/5xv2LD2kOCP3265PuNcSMigb5DwH8XlxkRpuPteLDX88d/lbVM3SPgMAiToDq8anWr9JWjnNv C1UyCL8u03HZu4eGJ0vF8k9jE+VhGxWYk6jHbA6COZSZHmIu3X6FoCZvyh1L6gr1Gp56zAUJN11 58ZkC6jUY7vgscDXAWLsb69KuSGNdVMQU7pKg8RYi9+J7MlyfFAipfcjVLJkIMBfSx8QgOTzapI tsInOyV4kgvteh+nUTUUlWAVAR9bTH15WHyPFE0O/Ym8VZ4x+S+2OSM90+rxVtxXp/FSEOg3KIP GcZEgdRnFRAS0wMDy4g== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDI5MDA0NSBTYWx0ZWRfX5wk6SNR9/9Rj kJ2vX2nAbbciNEq/ce3+3xnOejaR3Kz+oY0WgDtbPft+rJhj7n6xdL1qXKe5+/bSk3GYzGVDhKP ypBpDlQD2ugdSdlaClv0i7mYC4aBByQ= X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-29_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 bulkscore=0 spamscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 suspectscore=0 phishscore=0 malwarescore=0 priorityscore=1501 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610190000 definitions=main-2610290045 On Thu, Oct 29, 2026 at 03:48:45PM +0800, Zhanpeng Zhang wrote: > SSE delivery is independent of normal S-mode interrupts. Firmware may also > retain an event registration until Linux explicitly unregisters it. A hart > must therefore stop accepting SSE events before Linux stops servicing the > registered handler. > > Mask SSE on the local hart before panic stop, CPU stop, restart, poweroff, > and crash shutdown paths. This prevents firmware from entering Linux-owned > handler state after the corresponding CPU or kernel context is no longer > valid. > > A crash kernel cannot identify or take ownership of registrations > inherited from the crashed kernel. Reject a later normal kexec while such > SSE state may still exist, rather than transferring unknown firmware state > to another kernel. > > The restriction is deliberately based on firmware SSE availability, not > CONFIG_RISCV_SBI_SSE or registrations made by the crash kernel. Disabling > SSE in the crash kernel does not establish that registrations left by the > crashed kernel are absent. Consequently, normal kexec from a crash kernel > is also rejected when firmware advertises SSE but no registrations were > actually left behind. This conservative restriction remains until a safe > way to establish or clear inherited firmware state is available. > > Link: https://lore.kernel.org/r/as7-3PbWDxygadnJ@hu-himchau-blr.qualcomm.com/ > Reviewed-by: Himanshu Chauhan > Signed-off-by: Zhanpeng Zhang > --- > arch/riscv/kernel/machine_kexec.c | 11 +++++++++++ > arch/riscv/kernel/reset.c | 18 ++++++++++++++++++ > arch/riscv/kernel/smp.c | 17 +++++++++++++++++ > 3 files changed, 46 insertions(+) > > diff --git a/arch/riscv/kernel/machine_kexec.c b/arch/riscv/kernel/machine_kexec.c > index 738df176ff6..24e7affae70 100644 > --- a/arch/riscv/kernel/machine_kexec.c > +++ b/arch/riscv/kernel/machine_kexec.c > @@ -14,10 +14,13 @@ > #include /* For set_memory_x() */ > #include /* For unreachable() */ > #include /* For cpu_down() */ > +#include > #include > #include > #include > > +#include > + > /* > * machine_kexec_prepare - Initialize kexec > * > @@ -36,6 +39,13 @@ machine_kexec_prepare(struct kimage *image) > unsigned int control_code_buffer_sz = 0; > int i = 0; > > + /* A crash kernel cannot tear down registrations inherited from firmware. */ > + if (is_kdump_kernel() && image->type != KEXEC_TYPE_CRASH && > + riscv_sse_available()) { > + pr_err("Normal kexec from a crash kernel is unsupported with SSE\n"); > + return -EOPNOTSUPP; I think I had pointed this out in v10 also. This rejects a normal kexec from any kdump kernel whenever firmware merely advertises SSE, regardless of CONFIG_RISCV_SBI_SSE or whether anything is registered. Can you check if its breaking kexec() with SSE just being advertised? Regards Himanshu > + } > + > /* Find the Flattened Device Tree and save its physical address */ > for (i = 0; i < image->nr_segments; i++) { > if (image->segment[i].memsz <= sizeof(fdt)) > @@ -127,6 +137,7 @@ void > machine_crash_shutdown(struct pt_regs *regs) > { > local_irq_disable(); > + riscv_sse_mask_current_hart(); > > /* shutdown non-crashing cpus */ > crash_smp_send_stop(); > diff --git a/arch/riscv/kernel/reset.c b/arch/riscv/kernel/reset.c > index 14eb08a6db8..fdab37e7ae5 100644 > --- a/arch/riscv/kernel/reset.c > +++ b/arch/riscv/kernel/reset.c > @@ -6,6 +6,20 @@ > #include > #include > #include > +#include > + > +#include > + > +#ifndef CONFIG_SMP > +void __noreturn panic_smp_self_stop(void) > +{ > + riscv_sse_mask_current_hart(); > + local_irq_disable(); > + > + for (;;) > + cpu_relax(); > +} > +#endif > > static void __noreturn default_power_off(void) > { > @@ -18,6 +32,8 @@ EXPORT_SYMBOL(pm_power_off); > > void machine_restart(char *cmd) > { > + riscv_sse_mask_current_hart(); > + > /* > * UpdateCapsule() depends on the system being reset via ResetSystem(). > */ > @@ -30,12 +46,14 @@ void machine_restart(char *cmd) > > void machine_halt(void) > { > + riscv_sse_mask_current_hart(); > do_kernel_power_off(); > default_power_off(); > } > > void machine_power_off(void) > { > + riscv_sse_mask_current_hart(); > do_kernel_power_off(); > default_power_off(); > } > diff --git a/arch/riscv/kernel/smp.c b/arch/riscv/kernel/smp.c > index eddbc3ad06c..9ad38df4827 100644 > --- a/arch/riscv/kernel/smp.c > +++ b/arch/riscv/kernel/smp.c > @@ -22,10 +22,13 @@ > #include > #include > #include > +#include > > #include > #include > #include > +#include > +#include > > enum ipi_message_type { > IPI_RESCHEDULE, > @@ -78,8 +81,18 @@ int riscv_hartid_to_cpuid(unsigned long hartid) > return -ENOENT; > } > > +void __noreturn panic_smp_self_stop(void) > +{ > + riscv_sse_mask_current_hart(); > + local_irq_disable(); > + > + for (;;) > + cpu_relax(); > +} > + > static void ipi_stop(void) > { > + riscv_sse_mask_current_hart(); > set_cpu_online(smp_processor_id(), false); > while (1) > wait_for_interrupt(); > @@ -90,6 +103,7 @@ static atomic_t waiting_for_crash_ipi = ATOMIC_INIT(0); > > static inline void ipi_cpu_crash_stop(unsigned int cpu, struct pt_regs *regs) > { > + riscv_sse_mask_current_hart(); > crash_save_cpu(regs, cpu); > > atomic_dec(&waiting_for_crash_ipi); > @@ -253,6 +267,8 @@ void smp_send_stop(void) > { > unsigned long timeout; > > + riscv_sse_mask_current_hart(); > + > if (num_online_cpus() > 1) { > cpumask_t mask; > > @@ -300,6 +316,7 @@ void crash_smp_send_stop(void) > return; > > cpus_stopped = 1; > + riscv_sse_mask_current_hart(); > > /* > * If this cpu is the only one alive at this point in time, online or > -- > 2.50.1 (Apple Git-155) >