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Thu, 29 Oct 2026 14:18:51 -0700 Received: from nvidia.com (10.127.8.9) by mail.nvidia.com (10.129.68.7) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.2.2562.56 via Frontend Transport; Thu, 29 Oct 2026 14:18:49 -0700 Date: Thu, 29 Oct 2026 14:18:46 -0700 From: Nicolin Chen To: Mostafa Saleh CC: , , , , , , , , , , , , , , , , , Jean-Philippe Brucker Subject: Re: [PATCH v9 10/25] iommu/arm-smmu-v3-kvm: Add SMMUv3 driver Message-ID: References: <20261015200903.2735565-1-smostafa@google.com> <20261015200903.2735565-11-smostafa@google.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261015200903.2735565-11-smostafa@google.com> X-NV-OnPremToCloud: ExternallySecured X-EOPAttributedMessage: 0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: SJ5PEPF000001C9:EE_|DM4PR12MB6661:EE_ X-MS-Office365-Filtering-Correlation-Id: 7759ec23-fafc-4092-5752-08df360246dc X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|376014|36860700016|1800799024|23010399003|7416014|82310400026|261021121427099003|261021135927099003|261009223027099003|10067099003|56012099006|261026121527099003|3023799007|18002099003|22082099003|11063799006|4143699003; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: VpJaBdWm+q2jRlZ+ySwJYST6rdqFlN5IPi+t16e03cpZH5U1zXAS6nuoouDitfVfbaTTTWkBRi1F1S5+MAYPxVYqI3lRS3jTtfs4fla7mqOTF9GeocPyOyB2ESEWyaBu5hBn8Bz3r5t4+3oGXdcYP/PjnpVfUs4MdWIzekYPbTqR09+ufVLNr7I/V+9EbyIjFTrXR9GYtx0ka5piYIke/GjfTLV0nKYw9++tSLfzAXy5VtciMTjA6TUEIpxar+5+LvigLWM6sIV4Ax0cYF0G63bLLO2t1yzL5NHE6i1WIxeo43NeSqx7ebmjA+epzeMnlKJaz9GYOJS+dxz449O+Atil5NofJ8ZUj7l4k7lTpbp7m0JrG70nkGQD6ifb2/FJwgo34VOXw9JzJWkUXX+74RsP1s0ae6JFD0+m+ADyVKHIKR1Bq/xDA/KLgCuHVEcp X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 29 Oct 2026 21:19:11.6333 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 7759ec23-fafc-4092-5752-08df360246dc X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ5PEPF000001C9.namprd05.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: DM4PR12MB6661 On Thu, Oct 15, 2026 at 08:08:41PM +0000, Mostafa Saleh wrote: > From: Jean-Philippe Brucker > > Add the skeleton of the Arm SMMUv3 driver at EL2, and build the shared > IDR/STE code and lib/hweight.o into the hypervisor. > > The kernel driver, added next, fills an array describing the SMMUv3s in > the system and hands it to the hypervisor. At init the hypervisor takes > ownership of the array and of the SMMU MMIO regions, so the host cannot > change either after de-privilege. > > Signed-off-by: Jean-Philippe Brucker > Signed-off-by: Mostafa Saleh Reviewed-by: Nicolin Chen With some nits: > +/** > + * struct hyp_arm_smmu_v3_device - SMMUv3 instance owned by the hypervisor > + * @mmio_addr: Physical address of the SMMU registers > + * @mmio_size: Size of the register region > + * @base: Hypervisor virtual address of the registers > + * @features: ARM_SMMU_FEAT_* bits > + * @options: ARM_SMMU_OPT_* bits > + * @oas: Output address size > + * @pgsize_bitmap: Supported page sizes > + * @sid_bits: Number of StreamID bits Better drop those tabs, following Documentation/doc-guide/kernel-doc.rst Structure, union, and enumeration documentation: /** * struct struct_name - Brief description. * @member1: Description of member1. * @member2: Description of member2. * One can provide multiple line descriptions * for members. * * Description of the structure. */ > + * > + * @mmio_addr, @mmio_size and ARM_SMMU_FEAT_COHERENCY are filled by the host > + * before de-privilege, the rest by the hypervisor driver. > + */ > +struct hyp_arm_smmu_v3_device { > + phys_addr_t mmio_addr; > + size_t mmio_size; > + void __iomem *base; > + u32 features; > + u32 options; > + unsigned long oas; > + unsigned long pgsize_bitmap; > + unsigned int sid_bits; I'd drop the tabs too. Nicolin