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Thu, 29 Oct 2026 18:58:40 +0000 Date: Thu, 29 Oct 2026 11:58:35 -0700 From: Alison Schofield To: Srirangan Madhavan CC: Bjorn Helgaas , Dave Jiang , Davidlohr Bueso , Ira Weiny , Jonathan Cameron , Vishal Verma , , , , Li Ming , "Alex Williamson" , , , Sai Yashwanth Reddy Kancherla , Vishal Aslot , Manish Honap , Jiandi An , Richard Cheng , Subject: Re: [PATCH v16 00/18] PCI/CXL: Add CXL reset support for Type 2 devices Message-ID: References: <20261029145703.2185231-1-smadhavan@nvidia.com> Content-Type: text/plain; charset="us-ascii" Content-Disposition: inline In-Reply-To: <20261029145703.2185231-1-smadhavan@nvidia.com> X-ClientProxiedBy: MW4PR03CA0226.namprd03.prod.outlook.com (2603:10b6:303:b9::21) To DS4PPF0BAC23327.namprd11.prod.outlook.com (2603:10b6:f:fc02::9) X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 X-MS-PublicTrafficType: Email X-MS-TrafficTypeDiagnostic: DS4PPF0BAC23327:EE_|IA4PR11MB9180:EE_ X-MS-Office365-Filtering-Correlation-Id: ca00f338-33fe-431f-c9cc-08df35eea4d8 X-LD-Processed: 46c98d88-e344-4ed4-8496-4ed7712e255d,ExtAddr X-MS-Exchange-SenderADCheck: 1 X-MS-Exchange-AntiSpam-Relay: 0 X-Microsoft-Antispam: BCL:0;ARA:13230040|23010399003|376014|1800799024|7416014|366016|260925021311599003|260925022911599003|260925021911599003|11063799006|5023799004|56012099006|261009223027099003|261026140227099003|261026121527099003|261022075727099003|261028144727099003|10067099003|261022113327099003|261022105027099003|261021121427099003|261021123027099003|22082099003|18002099003|6133799003|3023799007; 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It disables CXL.cache, performs > supported cache writeback, initiates CXL Reset with Memory Clear, and > restores cached HDM decoder and CXL Device DVSEC state before PCI use > resumes. Active HDM ranges are reserved and CPU caches invalidated before > and after reset. The method remains limited to eligible single-function > devices with both CXL.cache and CXL.mem enabled. > > The reset sequence follows the CXL 4.0 specification [3], including > CXL.cache disable, optional cache writeback, CXL Reset Memory Clear, > ResetComplete polling, and ResetError reporting. Sections 9.7.2 and 9.7.3 > define the completion timeout encodings and reset access restrictions. > > The userspace ABI is the existing PCI reset interface: > > /sys/bus/pci/devices/.../reset_method > /sys/bus/pci/devices/.../reset > > Userspace selects "cxl_reset" in reset_method and triggers the reset > through reset. Following Dan's v6 feedback, this uses the PCI interface > instead of adding a memdev-specific sysfs ABI. > > For sysfs reset, the generic PCI path invokes the driver's reset_prepare() > callback when provided and disables PCI I/O, memory decoding, and bus > mastering. The CXL path reserves affected HDM ranges exclusively and > blocks IOMMU translations where applicable. It does not offline memory > or revoke mappings; it relies on CXL.mem users retaining conflicting > iomem resources while access remains active. > > Changes from v15 [1]: Srirangan, I notice you posted this v16 without responding to review feedback on v15. I've already compared v15 and v16 to see which review comments were addressed. However, that exercise is no substitute for responding to reviewers and resolving the discussions they initiate. Rather than me repeating the outstanding comments from v15, in v16, can you go back and respond to the v15 reviews before we proceed? Reference is the guidance in Documentation/process/submitting-patches.rst, under "Respond to review comments". CXL subsystem contributors also often append the reviewer's name to the end of each changelog item to identify whose feedback prompted the change. Thanks, Alison > - Split register discovery and cxl_rwsem preparation out of the HDM cache > patch. Share decoder register reads, read register pairs low then high, > and keep cache access and locking in HDM state helpers. > - Dropped Dave Jiang's and Li Ming's Reviewed-by tags from the decoder > unpacking and cache refresh patches (v15 patches 7 and 8; v16 patches 7 > and 9) because those changes need another review. > - Clarify the 16-way decoder interleave limit and incorporate the review > comments on decoder helpers and cache refresh. > - Keep a successfully read HDM snapshot if restoring PCI_COMMAND fails, > while reporting the failure. > - Clarify cache writeback timeout handling and report the effective reset > timeout. Keep all-ones config-read checks. > - Split cache preparation and state restoration into reusable helpers, > and simplify range error reporting. > - Allow the test-only region invalidation bypass for CXL reset. > - Explain the scope and duration of the global region lock. > - Reject virtual functions for CXL reset and CXL bus reset. > - Consolidate decoder commit polling, set Lock On Commit before commit, > and report HDM restore failures at the PCI restore path. > - Move the saved-PCI-state check into the CXL reset preparation helper. > - Move the standalone HDM decoder checks from cxl_test to KUnit. The test > layout follows Alison's proposed CXL KUnit series [4]; if it lands first, > these tests can be rebased onto that infrastructure. > > HDM caching now requires CXL.cache, CXL.mem, CXL Reset and Reset Memory > Clear capabilities. CXL bus reset state restoration uses that cache. > > CXL Reset requires a registered CPU cache clean/invalidate provider > and matching firmware, such as the separate SMCCC provider series [2]. > Without that provider, cxl_reset can be advertised while execution returns > -ENOTTY, unless the test-only CXL_REGION_INVALIDATION_TEST bypass is enabled. > > The KUnit suite checks HDM range boundaries, zero-size and uncommitted > state, lock and target-type decoding, and 12-way interleave. The unit test > suite passed on an earlier ARM64 test kernel. > Type 2 device reset cycles are also successful with this. The reset test > kernel also included the separate CXL bus cache maintenance patch. > > [1] https://lore.kernel.org/linux-cxl/20261011021422.3428136-1-smadhavan@nvidia.com/ > [2] https://lore.kernel.org/all/20260910082142.1522865-1-smadhavan@nvidia.com/T/ > [3] https://computeexpresslink.org/wp-content/uploads/2026/02/CXL-Specification_rev4p0_ver1p0_2026February26_clean_evalcopy_v2.pdf > [4] https://lore.kernel.org/all/cover.1791949910.git.alison.schofield@intel.com/ > > Srirangan Madhavan (18): > cxl: Clarify decoder interleave limit > cxl: Share CXL port upstream PCI device lookup > cxl: Move decoder declarations to shared header > cxl: Embed decoder configuration in a standalone structure > cxl: Introduce endpoint HDM decoder settings > cxl: Move HDM decoder helpers to built-in code > cxl: Share HDM decoder register unpacking > cxl: Move cxl_rwsem into built-in code > cxl: Refresh cached PCI HDM decoder settings > cxl: Build register block helpers into the kernel > PCI/CXL: Cache endpoint HDM state during PCI enumeration > PCI/CXL: Add CXL Device Reset sequencing > cxl: Validate and synchronize HDM ranges around reset > PCI/CXL: Reject reset with unsafe function scope > PCI/CXL: Restore CXL state after PCI reset > PCI/CXL: Expose CXL Reset as a PCI reset method > PCI/CXL: Restore CXL state after CXL bus reset > cxl: Add KUnit checks for HDM decoder unpacking > > MAINTAINERS | 1 + > drivers/cxl/.kunitconfig | 4 + > drivers/cxl/Kconfig | 18 +- > drivers/cxl/Makefile | 1 + > drivers/cxl/acpi.c | 26 +- > drivers/cxl/core/Makefile | 2 +- > drivers/cxl/core/atl.c | 4 +- > drivers/cxl/core/core.h | 15 + > drivers/cxl/core/hdm.c | 273 ++++------ > drivers/cxl/core/hdm_regs.c | 419 ++++++++++++++ > drivers/cxl/core/hdm_state.c | 408 ++++++++++++++ > drivers/cxl/core/pci.c | 70 ++- > drivers/cxl/core/port.c | 68 ++- > drivers/cxl/core/region.c | 102 ++-- > drivers/cxl/core/regs.c | 9 + > drivers/cxl/cxl.h | 46 +- > drivers/cxl/pci.c | 2 +- > drivers/cxl/port.c | 4 +- > drivers/cxl/tests/Makefile | 5 + > drivers/cxl/tests/hdm_unpack_kunit.c | 90 +++ > drivers/pci/Makefile | 1 + > drivers/pci/bus.c | 1 + > drivers/pci/cxl.c | 784 +++++++++++++++++++++++++++ > drivers/pci/pci.c | 12 + > drivers/pci/pci.h | 29 + > drivers/pci/probe.c | 1 + > include/cxl/cxl.h | 60 +- > include/cxl/hdm.h | 109 ++++ > include/cxl/pci.h | 13 + > include/linux/pci.h | 8 +- > include/uapi/linux/pci_regs.h | 14 + > tools/testing/cxl/Kbuild | 1 - > tools/testing/cxl/test/cxl.c | 158 +++--- > 33 files changed, 2337 insertions(+), 421 deletions(-) > create mode 100644 drivers/cxl/.kunitconfig > create mode 100644 drivers/cxl/core/hdm_regs.c > create mode 100644 drivers/cxl/core/hdm_state.c > create mode 100644 drivers/cxl/tests/Makefile > create mode 100644 drivers/cxl/tests/hdm_unpack_kunit.c > create mode 100644 drivers/pci/cxl.c > create mode 100644 include/cxl/hdm.h > > > base-commit: fef22d37d47043b63e4007f2f5fe762fa21fae0c > -- > 2.43.0 >