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[199.106.103.52]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1ac19f4a04esm16412510c88.15.2026.10.31.06.28.29 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sat, 31 Oct 2026 06:28:32 -0700 (PDT) Date: Sat, 31 Oct 2026 21:28:26 +0800 From: Shawn Guo To: Krishna Chaitanya Chundru Cc: Konrad Dybcio , Rob Herring , Bjorn Andersson , Krzysztof Kozlowski , Conor Dooley , Bartosz Golaszewski , Yu Zhang , Shuai Zhang , devicetree@vger.kernel.org, linux-arm-msm@vger.kernel.org, linux-kernel@vger.kernel.org, Konrad Dybcio , Abel Vesa , Bartosz Golaszewski Subject: Re: [PATCH RFC v3 3/5] arm64: dts: qcom: nord-ride-embedded: Enable PCIe controllers and PHY Message-ID: References: <20261021022921.2053957-1-shengchao.guo@oss.qualcomm.com> <20261021022921.2053957-4-shengchao.guo@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=iso-8859-1 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: X-Proofpoint-ORIG-GUID: QiGf_murEnNuC8o_8rqC7zq2h4TDxVSW X-Proofpoint-GUID: QiGf_murEnNuC8o_8rqC7zq2h4TDxVSW X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMDMxMDA1MyBTYWx0ZWRfXwMRvryVF+hEh sO4tDArRZpkfgM2fVYvN54CTpmhSB4bBckHiyiZu116YA9Dxin1zjVjgxX1vykQYbqTAv9y9CuG k9mpL2XRivleMnCxHKAb6RLtVHmQqS4ODXrJaqu0Y1bS3Ko9tOCEd4Qv2Za+yUWWFbj6wLKoye8 VLYaw5O9htcD0fUZdXyKUBqmbl7Cr7Es/iir/ZkCsgI99lAJaza7QMVE0+8BDSr1QJQONKDio5t DdCdryAeeKQkD0o3DitTCt8r8ZjhgHjaZNKAVY43bD8cSjkG9KqQZTxM9tanMqLDj7fgGNk89aA Jpt2SA8cvHNX6gbLUHxVthD7nktw9d/ajel/avXfZhljonh4nuYmbS+AcvH4KyyxG47h8bB4OW/ gvDCYERfm/RQGsM1Jna4yf1+Vhkkl1cbOT5p9LjgxZsd4Xk3pv/58GIBj5tg+2D7JrZ0JrUCpdW 1wN4PQB+H144FXY9Saw== X-Proofpoint-Spam-Info: AW1haW4tMjYxMDMxMDA1MyBTYWx0ZWRfX54vIQlPkjatP yX8Gnm0j7NHqfI+GurXNHl2eML1RRQV82f0F59ZPIDR55TnvRvuT4z+RR1eKknXOZsWnflczVlC +rS+yUP2Jt0PdrbrEdfnphNSbT0/Kxs= X-Authority-Analysis: v=2.4 cv=cfVHPXDM c=1 sm=1 tr=0 ts=6ae5ed02 cx=c_pps a=Uww141gWH0fZj/3QKPojxA==:117 a=b9+bayejhc3NMeqCNyeLQQ==:17 a=8nJEP1OIZ-IA:10 a=660iZSQnnn4A:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=YMgV9FUhrdKAYTUUvYB2:22 a=EUspDBNiAAAA:8 a=6Qp4BPjpy_d1hweZHL0A:9 a=3ZKOabzyN94A:10 a=wPNLvfGTeEIA:10 a=PxkB5W3o20Ba91AHUih5:22 X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-10-31_03,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 impostorscore=0 phishscore=0 lowpriorityscore=0 clxscore=1015 adultscore=0 priorityscore=1501 spamscore=0 bulkscore=0 suspectscore=0 malwarescore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2610310053 On Sat, Oct 31, 2026 at 03:50:09PM +0530, Krishna Chaitanya Chundru wrote: > > > On 10/21/2026 7:59 AM, Shawn Guo wrote: > > From: Krishna Chaitanya Chundru > > > > The Nord Ride Embedded board routes all four PCIe links, so enable > > pcie0-pcie3 and the QMP PHY, supply the per-port PHY and PLL rails, and > > describe the PERST# and WAKE# lines of each root port. > > > > Signed-off-by: Krishna Chaitanya Chundru > > Reviewed-by: Konrad Dybcio > > Reviewed-by: Abel Vesa > > Reviewed-by: Bartosz Golaszewski > > Signed-off-by: Shawn Guo > > --- > > .../boot/dts/qcom/nord-ride-embedded.dts | 49 +++++++++++++++++++ > > 1 file changed, 49 insertions(+) > > > > diff --git a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > > index 49635695f832..fcc07226db8b 100644 > > --- a/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > > +++ b/arch/arm64/boot/dts/qcom/nord-ride-embedded.dts > > @@ -366,6 +366,55 @@ vreg_l3l_1p8: ldo3 { > > }; > > }; > > > > +&pcie_phy { > > + vdda-phy-a-supply = <&vreg_l6a_1p2>; > > + vdda-phy-b-supply = <&vreg_l4a_1p2>; > > + vdda-phy-c-supply = <&vreg_l4a_1p2>; > > + vdda-phy-d-supply = <&vreg_l4a_1p2>; > > + vdda-pll-a-supply = <&vreg_l1e_0p9>; > Hi Shawn, > > I did a mistake while sharing these changes, pll supply for b, c, d should be > l2e instead of l1e. > -    vdda-pll-b-supply = <&vreg_l1e_0p9>; > -    vdda-pll-c-supply = <&vreg_l1e_0p9>; > -    vdda-pll-d-supply = <&vreg_l1e_0p9>; > +    vdda-pll-b-supply = <&vreg_l2e_0p9>; > +    vdda-pll-c-supply = <&vreg_l2e_0p9>; > +    vdda-pll-d-supply = <&vreg_l2e_0p9>; > > Can you update them as this patch is not applied yet. Sure! I checked schematics and RRD board needs the same correction. Shawn