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charset=us-ascii Content-Disposition: inline In-Reply-To: <20261030094024.3226356-1-chunyan.zhang@linux.spacemit.com> User-Agent: Mutt/2.4.1 (2026-07-04) Hi, On 2026-10-30 17:40, Chunyan Zhang wrote: > Describe the DWC3 controller and its USB 2.0 PHY for USB3 port A > of the K3 SoC. > > Only the U2 lane is described: Port A's SuperSpeed PHY has no driver > yet, so the port runs at high-speed (maximum-speed = "high-speed"). > > Enable USB3 port A with dr_mode = "peripheral", so it can be used as > a USB device. > > Signed-off-by: Chunyan Zhang > --- > arch/riscv/boot/dts/spacemit/k3-pico-itx.dts | 9 ++++++ > arch/riscv/boot/dts/spacemit/k3.dtsi | 30 ++++++++++++++++++++ > 2 files changed, 39 insertions(+) > > diff --git a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > index b084a35aa00e..74d4fdf9e405 100644 > --- a/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > +++ b/arch/riscv/boot/dts/spacemit/k3-pico-itx.dts > @@ -323,6 +323,15 @@ &usb2_phy { > status = "okay"; > }; > > +&usb3a_u2phy { > + status = "okay"; > +}; > + > +&usb3a { > + dr_mode = "peripheral"; > + status = "okay"; > +}; > + > &usb3d_u2phy { > status = "okay"; > }; > diff --git a/arch/riscv/boot/dts/spacemit/k3.dtsi b/arch/riscv/boot/dts/spacemit/k3.dtsi > index c3f2dce0969c..220dfe29bb78 100644 > --- a/arch/riscv/boot/dts/spacemit/k3.dtsi > +++ b/arch/riscv/boot/dts/spacemit/k3.dtsi > @@ -630,6 +630,36 @@ gmac2_axi_setup: stmmac-axi-config { > }; > }; > > + usb3a: usb@cad00000 { Please move this after the eth2 node, so that the node addresses are kept sorted. > + compatible = "spacemit,k3-dwc3"; > + reg = <0x0 0xcad00000 0x0 0x10000>; > + interrupts = <118 IRQ_TYPE_LEVEL_HIGH>; > + interrupt-parent = <&saplic>; > + clocks = <&syscon_apmu CLK_APMU_USB3_PORTA_BUS>; > + clock-names = "usbdrd30"; > + resets = <&syscon_apmu RESET_APMU_USB3_A_AHB>, > + <&syscon_apmu RESET_APMU_USB3_A_VCC>, > + <&syscon_apmu RESET_APMU_USB3_A_PHY>; > + reset-names = "ahb", "vcc", "phy"; > + phys = <&usb3a_u2phy>; > + phy-names = "usb2-phy"; Please move the PHYs definition to the board level, matching was it is done for the other USB3 ports, as other boards might have different PHY configuration. > + phy_type = "utmi"; > + snps,dis_enblslpm_quirk; > + snps,dis_u2_susphy_quirk; > + snps,dis-del-phy-power-chg-quirk; > + snps,dis-tx-ipgap-linecheck-quirk; > + maximum-speed = "high-speed"; I think the maximum-speed property should also be moved to the board level, as its value depends on the PHYs configuration. > + status = "disabled"; > + }; Any reason not to define the snps,parkmode-disable-ss-quirk property? It is defined for the other USB3 ports, as well as for the USB3 A port in the vendor kernel > + > + usb3a_u2phy: phy@cad20000 { > + compatible = "spacemit,k3-usb2-phy"; > + reg = <0x0 0xcad20000 0x0 0x200>; > + clocks = <&syscon_apmu CLK_APMU_USB3_PORTA_BUS>; > + #phy-cells = <0>; > + status = "disabled"; > + }; > + > pdma: dma-controller@d4000000 { > compatible = "spacemit,k3-pdma"; > reg = <0x0 0xd4000000 0x0 0x4000>; Otherwise looks good. Regards Aurelien -- Aurelien Jarno GPG: 4096R/1DDD8C9B aurelien@aurel32.net http://aurel32.net