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[129.46.96.20]) by smtp.gmail.com with ESMTPSA id a92af1059eb24-1aed79b3dfcsm27427782c88.12.2026.11.01.19.32.14 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Sun, 01 Nov 2026 19:32:14 -0800 (PST) Date: Sun, 1 Nov 2026 19:32:12 -0800 From: Peter Chen To: Faisal Hassan Cc: linux-usb@vger.kernel.org, Krzysztof Kozlowski , Thinh Nguyen , Krishna Kurapati , Sriram Dash , Greg Kroah-Hartman , Philipp Zabel , linux-kernel@vger.kernel.org, linux-arm-msm@vger.kernel.org Subject: Re: [PATCH v4 5/7] usb: dwc3: qcom: Support broken suspend for SA8255P Message-ID: References: <3a4bdffa9101fa81e4511d84c5a3ddd0b972efe2.1793212717.git.faisal.hassan@oss.qualcomm.com> X-Mailing-List: linux-kernel@vger.kernel.org List-Id: List-Post: List-Help: List-Subscribe: List-Unsubscribe: List-Owner: Precedence: list MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Disposition: inline In-Reply-To: <3a4bdffa9101fa81e4511d84c5a3ddd0b972efe2.1793212717.git.faisal.hassan@oss.qualcomm.com> X-Proofpoint-GUID: GUasoA5hDsLR1IkV7TA4UN6PCg8LAjNq X-Proofpoint-ORIG-GUID: GUasoA5hDsLR1IkV7TA4UN6PCg8LAjNq X-Authority-Analysis: v=2.4 cv=S5RMU4sP c=1 sm=1 tr=0 ts=6ae80440 cx=c_pps a=PfFC4Oe2JQzmKTvty2cRDw==:117 a=ouPCqIW2jiPt+lZRy3xVPw==:17 a=kj9zAlcOel0A:10 a=zJRp6_cAMcgA:10 a=s4-Qcg_JpJYA:10 a=VkNPw1HP01LnGYTKEx00:22 a=u7WPNUs3qKkmUXheDGA7:22 a=yOCtJkima9RkubShWh1s:22 a=VwQbUJbxAAAA:8 a=pGLkceISAAAA:8 a=PcBk4QqV-VHVs7bFY3sA:9 a=CjuIK1q_8ugA:10 a=6Ab_bkdmUrQuMsNx7PHu:22 X-Proofpoint-Spam-Info: AW1haW4tMjYxMTAyMDAxMyBTYWx0ZWRfXz0wL1dzp4rs3 8jkJ0kIFfJmlEMuMChL0FSzICJL+4u2ZC8fRGBRinCxCZAjjqENGbe+7HQPPaIw8ad/SwuJma3t 9QK+oVgq5l4buZ4LA8Fw0YxO/aDRmOQ= X-Proofpoint-Spam-Details-Enc: AW1haW4tMjYxMTAyMDAxMyBTYWx0ZWRfX41niAoUmmub0 zWCwUDWJxp+WiRlaXrqnqrDaofQLlwdtc/ePh/vaIltK1Ut3fZjo4+WuGpjigHDx7d/wCsUra40 vctBDGB+wc8vjcR9bPpqeALRbm/uWlZGSBUIkziNfDtsJ2Po/2BHiWfyzOh+D7DjrQkIwYgNNTJ VnXHkYwgEbjiz6CutzccxTvNs0qRslwNViqCAr9Y0/RwCEPyO5Ai9QX9CtA4GaLd7wawaGkQ9UM UquWYgZEwEPwhnH03UgCg6loaZPQ+o1EdSmaMIe21N4qeHme1+9DT9po3HH3jaGFPx8i4YMHJXM evmaUHUQtmT/WIrLPJE3/JRlJTCkqCPYspF5x588kfz+IplYUoufnRxpUaE5HUlf+ffp+TAJo5X ZqaRJIy+X8s1g70ON8cXoGyzOEssoJhxdrdDZ1yGes+2esf64ME8kZL5aocMMse2PYe4NCDIrsW eypXrGNx4FuPPSOH2Ew== X-Proofpoint-Virus-Version: vendor=baseguard engine=ICAP:2.0.293,Aquarius:18.0.1176,Hydra:6.1.138,FMLib:17.12.100.49 definitions=2026-11-02_01,2026-10-21_02,2025-10-01_01 X-Proofpoint-Spam-Details: rule=outbound_notspam policy=outbound score=0 spamscore=0 impostorscore=0 bulkscore=0 clxscore=1015 lowpriorityscore=0 malwarescore=0 phishscore=0 adultscore=0 priorityscore=1501 suspectscore=0 classifier=typeunknown authscore=0 authtc= authcc= route=outbound adjust=0 reason=mlx scancount=1 engine=8.22.0-2610300000 definitions=main-2611020013 On 26-10-29 00:29:35, Faisal Hassan wrote: > During APPS Suspend, the clock controller unit disables all clocks > to the CPU and subsystems, causing the controller to enter the > Power-On Reset (POR) state. This results in the loss of > Qscratch programming. > > Upon APPS Resume, the USB controller does not have the proper > PIPE_UTMI_CLK_SEL or VBUS_VALID. Hence, if only the High-Speed > PHY is used for a controller capable of SuperSpeed operations, > the controller will assume it should use the USB3 PHY and not > the HS PHY as configured before APPS Suspend. This behavior > disrupts the normal operation of the USB controller. Similarly, > if the controller was operating in device mode prior to > APPS suspend, and VBUS_VALID signal is not set after APPS resume, > this will cause the PHYs to transition into the suspend state. > This behavior disrupts the normal operation of the USB controller. > > Address the issues by ensuring that the PIPE_UTMI_CLK_SEL and > VBUS_VALID are handled properly after the system resumes from > APPS Suspend. This is crucial for maintaining the correct > operational state of the USB controller and preventing > unintended suspensions of the PHYs. > > Also, as the controller is starting from POR state, make > sure the controller Reset is performed. > > Because the controller is reset on every system resume, the > Qscratch restore is done whether or not wakeup was enabled, and > dwc3 core is told via needs_full_reinit to fully re-initialize the > core on system resume even in host mode with wakeup enabled. Wakeup > on this platform comes from the PHY interrupts routed through PDC, > not from the controller staying powered. VBUS_VALID is only forced > outside host mode, matching what probe does. > > The XHCI controller is reset by the same event, so also set the > xhci_reset_on_resume dwc3 property. dwc3 passes it on to the xhci-plat > device as xhci-reset-on-resume-quirk, which makes xhci-plat set > XHCI_RESET_ON_RESUME. > > Also make the .prepare callback return 0 on these platforms. A > runtime-suspended device in device mode would otherwise be left in > place across system sleep (direct_complete), skipping the system > resume callback and with it the reset and Qscratch restore. Faisal, there are several issues in this patch, would you try to split them? - XHCI_RESET_ON_RESUME quirk support for dwc3 - PIPE_UTMI_CLK_SEL restore after system resume, there is a similar submission recently [1] - VBUS override restore after system resume - The improvement for system resume dues to HW POR or lost of power. [1]: https://lore.kernel.org/all/20261027-dwc3-utmi-resume-v1-1-ca9f0aa65783@gmail.com/ > > struct dwc3_qcom { > struct device *dev; > void __iomem *qscratch_base; > @@ -86,6 +90,13 @@ struct dwc3_qcom { > struct icc_path *icc_path_apps; > > enum usb_role current_role; > + > + bool broken_suspend; > + bool ignore_pipe_clk; > +}; > + > +static const struct dwc3_qcom_priv_data sa8255p_dwc3_qcom_priv_data = { > + .broken_suspend = true, > }; Why you consider it is "broken", or is it a normal resume recovery due to lost of status for controller and PHY? Why other SoCs don't need it? > static int dwc3_qcom_prepare(struct device *dev) > { > struct dwc3 *dwc = dev_get_drvdata(dev); > + struct dwc3_qcom *qcom = to_dwc3_qcom(dwc); > + > + /* > + * The controller loses power across system suspend, so the system > + * resume callback must always run to reset and reprogram it. Don't > + * let the PM core leave a runtime-suspended device as-is. > + */ > + if (qcom->broken_suspend) > + return 0; Why we need this? I see dwc3 core do dwc3_core_init_for_resume at device mode during the resume. > > return dwc3_pm_prepare(dwc); > } -- Thanks, Peter Chen