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dkim=none (message not signed) header.d=none;dmarc=none action=none header.from=nvidia.com; Received: from BL0PR12MB2370.namprd12.prod.outlook.com (2603:10b6:207:47::27) by SJ1PR12MB6340.namprd12.prod.outlook.com (2603:10b6:a03:453::17) with Microsoft SMTP Server (version=TLS1_2, cipher=TLS_ECDHE_RSA_WITH_AES_256_GCM_SHA384) id 15.21.592.8; Tue, 3 Nov 2026 07:17:48 +0000 Received: from BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8]) by BL0PR12MB2370.namprd12.prod.outlook.com ([fe80::86cf:c3ec:2cf5:74c8%5]) with mapi id 15.21.0592.007; Tue, 3 Nov 2026 07:17:46 +0000 Date: Tue, 3 Nov 2026 15:17:41 +0800 From: Richard Cheng To: Li Ming Cc: dave@stgolabs.net, jic23@kernel.org, dave.jiang@intel.com, alison.schofield@intel.com, vishal.l.verma@intel.com, iweiny@kernel.org, linux-cxl@vger.kernel.org, linux-kernel@vger.kernel.org, kaihengf@nvidia.com, kobak@nvidia.com, newtonl@nvidia.com, kristinc@nvidia.com Subject: Re: [PATCH] cxl/port: Unmask AER internal errors for VH endpoints Message-ID: References: <20261030095951.46080-1-icheng@nvidia.com> Content-Type: text/plain; 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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?WYJqRVRqWwSukd3cFQ2UPrrFv1IKO4MX1qZSvlWkc1fBKQabsR/C+9FlyVK4?= =?us-ascii?Q?WsDhRNuNjdFVXJibwPG9WKLY8ygMvQRuwG/YPCxf2somMEY7419sVQWnmI9F?= =?us-ascii?Q?b18l4pf1tVBK0zKJXfaBp4ZnfoA0+/vZN6NiFtEBywXAag/SerTLTuzmNf92?= =?us-ascii?Q?N8uKM+kD2OtKVHGLPgG6+lXJzpLNRVPaZ+rO89CdSd8/eysQf2Fndp3GY8JK?= =?us-ascii?Q?uMj02lS8q091jrUyyVbwd67YV/Wbc/APu7C8/b9ohItWynDC5wOovgqvmvLt?= =?us-ascii?Q?I7QkeghXs8lhuNfqAGgdKBmaGFsqenJx0aFeTM7kVDc9vZJfZ+ll0dm8FG1p?= =?us-ascii?Q?H655ksfq4zwSdXx23uIglrsTw9MeYu9YzvLAGKHkouh9b1MM+ag4rQ5g4DsK?= =?us-ascii?Q?UE5CzbfCn62S8RnpwmdCKUcqZPOMMdQXkITos0F2+N+k0TPMMnrWFk7xdJ5z?= =?us-ascii?Q?j+iUZG4Dfig7WiheEbotkVTi7zIuDJFFHDHij9RDPRoWe/NKkCJlpy0TKYuH?= =?us-ascii?Q?ASAzb/xundz4scSLTETn9CTYY9bFC5Z5hKZDyuDp8NHE8IAzEoA+T906lHs3?= =?us-ascii?Q?JC1CNyQBeeFJ3l2eMmH8iQshcP3W1EhQKUTFiYn9u6bIwjZ83dOgW40mpsMc?= =?us-ascii?Q?DGxezkrsYPTFf7ov99FAOn50GQuuXZgGoT4iXp1lbuEnsYRmrAhv+rwmI+rx?= =?us-ascii?Q?auq+8Hz2XNht9Hicyn/oTjjuFm73fTtR7MFCVIZwHeTGvlo6duSRa7x7/vgt?= =?us-ascii?Q?w9I9ke4HFdNx1AuFanlFS5TQwGIz30DQ3+mi9XAzwPE63WZkHAzwG6Hb/QXd?= =?us-ascii?Q?EL4nw4eXpBWfP7OY9ARsdLqL/4pPHDKBmDjJoYw8U/jrmE0MZrJ6fUtL0pqy?= =?us-ascii?Q?5OGLjpxApcsjuU1wL5llSqmPNhVboIYKaErDlyF0pEcZjWtZ4+UR18bNf6g5?= =?us-ascii?Q?fSLfuEJq972kUxnsXFwYyJxgnHl03+UX2Wz7xCHmYWoTXLqvd+iq3qZaZhzF?= =?us-ascii?Q?LdxefWYTAV7tpfIR6LiDLNdJAQ2ox0PWNTPv3TkLQywv7FsnhQuH42mPC4Ke?= =?us-ascii?Q?D1VY8iFKD7+fkhStcWBcMSzIAqMt7j75tYANl/x96NMdSTe2Ab0sQfD+v+JU?= =?us-ascii?Q?sdRHun6Bo29TdcDotWUr/Q/Hj34pjjpJ34k6S9QurTrOjN+/iOYnygsLTUPM?= =?us-ascii?Q?mSORkNryKyGr+fyT1nYn2YP1ZDnuQEhfHvIE2a1qBnOLEnbNLUv1XQXpI3Ja?= =?us-ascii?Q?SSPGHZPKqlykb9c6V27ZWdxcbx921s0vHxOWJJHY3clznfVOCQuXXtduOH3t?= =?us-ascii?Q?c9Nl2uOPMc4wtaB5YBUuuLeRRZVwSGXKAVnldRzqky2W/UYmEZEi5Pz1iByU?= =?us-ascii?Q?rCEQZhtqcABcSTkTWCY8sm23slBpLXbeRH8Pzji1BHGpdxbTjBGr2QXHkCRL?= =?us-ascii?Q?K8MyPSzJjjiR7Ch2cKr1V24Fgg+hM80CiNyWcF2d/pRkMsFtgT0j4w45KW21?= =?us-ascii?Q?yRaSjWZcFNouW9MnrGoRR4CvHzGHPhV77P1weghusMqrINDxSrhgcaAvXHNI?= =?us-ascii?Q?xc8cir6ROMuVI5KYV8ZrMgA9pUhXNdTBOTIllqReV8OV9G805RFc/xmQsx5d?= =?us-ascii?Q?+f1JwRUUJPFm5gDBTX7zYX1/6X2jefwMVTaAlU70rvA8IQKtpTSSF/Dvbm48?= =?us-ascii?Q?5M6jF7RFG5va9ihYlLCYY95nlE8In9vYtA57sAFJEZnXsEpy?= X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-Network-Message-Id: 2d105cf5-7d4b-427f-ae9d-08df397a8ef5 X-MS-Exchange-CrossTenant-AuthSource: BL0PR12MB2370.namprd12.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 07:17:46.0788 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: JBkkMWRHGJhkUsKkx+eFodm4Me07koaLrd+DvxXzPwDhnTjNASphwVskd6Fhgk227IBMfEjZ1RV7YlomahUJEg== X-MS-Exchange-Transport-CrossTenantHeadersStamped: SJ1PR12MB6340 On Sat, Oct 31, 2026 at 03:11:29AM +0800, Li Ming wrote: > On 10/30/2026 5:59 PM, Richard Cheng wrote: > > CXL protocol errors are reported through PCIe AER internal errors. > > Unmasking the endpoint's CXL RAS register alone leaves the AER internal > > errors masked, thus the notification can't reach the Root Port. > > > > Unmask AER internal errors during native endpoint RAS setup for VH > > devices. Allow cxl_port to use pci_aer_unmask_internal_errors() through > > its module-restricted export. > > > > Verified with QEMU mem-data-ecc injection: the Root Port AER interrupt > > fires, the CXL correctable-error trace is emitted, and the endpoint's > > CorrIntErr counter increments. > > I found the similiar implementation[1] in CXL RAS support for VH patchset[2], seems like it is under review. > Ohh ok, then I think we can drop this one. Thanks. > > [1]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-9-terry.bowman@amd.com/ > > [2]: https://lore.kernel.org/linux-cxl/20260902133933.2992457-1-terry.bowman@amd.com/ > > > Ming > > > > > Signed-off-by: Richard Cheng > > --- > > drivers/cxl/port.c | 7 +++++++ > > drivers/pci/pcie/aer.c | 3 ++- > > 2 files changed, 9 insertions(+), 1 deletion(-) > > > > diff --git a/drivers/cxl/port.c b/drivers/cxl/port.c > > index c48216e5078f..c94a310061b0 100644 > > --- a/drivers/cxl/port.c > > +++ b/drivers/cxl/port.c > > @@ -121,6 +121,13 @@ static int cxl_ras_unmask(struct cxl_port *port) > > orig_val, val); > > } > > > > + /* > > + * RCH errors are reported by the RCEC. VH endpoints report CXL > > + * protocol errors as PCIe AER internal errors. > > + */ > > + if (!is_cxl_restricted(pdev)) > > + pci_aer_unmask_internal_errors(pdev); > > + > > return 0; > > } > > > > diff --git a/drivers/pci/pcie/aer.c b/drivers/pci/pcie/aer.c > > index db4f607f889c..94eca22422b7 100644 > > --- a/drivers/pci/pcie/aer.c > > +++ b/drivers/pci/pcie/aer.c > > @@ -1287,7 +1287,8 @@ void pci_aer_unmask_internal_errors(struct pci_dev *dev) > > * Internal errors are too device-specific to enable generally, however for CXL > > * their behavior is standardized for conveying CXL protocol errors. > > */ > > -EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, "cxl_core"); > > +EXPORT_SYMBOL_FOR_MODULES(pci_aer_unmask_internal_errors, > > + "cxl_core,cxl_port"); > > > > #ifdef CONFIG_CXL_RAS > > bool is_aer_internal_error(struct aer_err_info *info) > > > > base-commit: f0c48323b0402349530abc60ea908b5f5f40c395 > >