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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: PU2cD42C6OPMSOGOPTKjdfPDnMQNGCn/3Qb4bJKoySfQn0wBVyNWa3WBfWPXHJMVWhBqbc+Qo9Qj8d+BLczZ5I5/1hTGON/LH0HwGRK2+nd/rFlVLa8XPzfswcvjbw4tIDfhIW7GBp/oF5zQ6KWUyHyX+RNbG9tGA2kTPjMhpMcvpk9rc/LN48+cKxowI9cAX4WBQGZc4eZyhxLg8m8U1hLkEI8RBAqW5Gi/87gHviISQLXpz0pC1COnnBa9cSI4U7wP31EymVFCc26z946XeA7/wodKPIEmcP2qbQHWdt3LNJKRrC9hxMAvyswQCeTyZUzblzuoVpSgnkt7X/BqBJwB2y1usQfuda9PRrrX33smVOtv/bKmPravpRqTinyDHNUOQH3/t6ss34t5VYxAlF6tWkSPaqsF4+lvFNyMOdvbL28OFtVXjctVIjZRKiJc X-OriginatorOrg: Nvidia.com X-MS-Exchange-CrossTenant-OriginalArrivalTime: 03 Nov 2026 18:44:55.3363 (UTC) X-MS-Exchange-CrossTenant-Network-Message-Id: 44111012-f6e2-4990-9c32-08df39da8dcf X-MS-Exchange-CrossTenant-Id: 43083d15-7273-40c1-b7db-39efd9ccc17a X-MS-Exchange-CrossTenant-OriginalAttributedTenantConnectingIp: TenantId=43083d15-7273-40c1-b7db-39efd9ccc17a;Ip=[216.228.117.160];Helo=[mail.nvidia.com] X-MS-Exchange-CrossTenant-AuthSource: SJ1PEPF000037AF.namprd03.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Anonymous X-MS-Exchange-CrossTenant-FromEntityHeader: HybridOnPrem X-MS-Exchange-Transport-CrossTenantHeadersStamped: CY1PR12MB9583 On Tue, Nov 03, 2026 at 10:33:43AM -0800, Nicolin Chen wrote: > cxl_reset_bus_function() reports "supported" to a probe after checking only > that the upstream bridge carries a CXL port DVSEC. The underlying bus reset > can still be unavailable, e.g. on a bus shared with other devices, so both > the reset_methods[] array and the reset_method sysfs node end up listing a > "cxl_bus" that is guaranteed to fail with -ENOTTY when it is attempted. > > Probe the underlying pci_dev_reset_slot_function() and then, if it is not > applicable, pci_parent_bus_reset(). These are the same two checks that the > actual reset runs, so a shared-bus CXL device no longer advertises a method > that can never succeed. > > Probing via pci_reset_bus_function() would not work: its cxl_sbr_masked() > check rejects every CXL port with a masked SBR, while the do-reset path in > this function unmasks the SBR before resetting. Such a port would wrongly > probe as unsupported. > > Move the port control register read above the probe branch as well, so that > probe runs the same checks. That read asserts no reset, and a failure means > the device cannot be reset this way, which is a probe-time answer. > > Also pass an explicit PCI_RESET_DO_RESET at the do-reset call site, since > probe is always false at that point. > > Fixes: 53c49b6e6dd2e ("PCI/CXL: Add 'cxl_bus' reset method for devices below CXL Ports") > Signed-off-by: Nicolin Chen Ah, I missed Jonathan's review tag during the split: https://lore.kernel.org/linux-iommu/20260926001311.7c4be583@jic23-hlaptop/ Jonathan, would you mind giving another review tag here? It's the exact same patch that you reviewed. Sorry for the inconvenience. Nicolin