From: Keith Busch <kbusch@kernel.org>
To: Liao Xuan <liaoxuan@open-hieco.net>
Cc: axboe@kernel.dk, hch@lst.de, sagi@grimberg.me,
linux-nvme@lists.infradead.org, linux-kernel@vger.kernel.org,
default avatarZheng Tan <tanzheng@kylinos.cn>
Subject: Re: [PATCH 1/3] nvme: Add adaptive PCIe link rate switching function
Date: Tue, 3 Nov 2026 12:08:15 -0700 [thread overview]
Message-ID: <auoxH197kQfUJGaE@kbusch-mbp> (raw)
In-Reply-To: <85a11a4085d04a2823c04059702630cf34abf6d4.1790134954.git.liaoxuan@open-hieco.net>
On Tue, Nov 03, 2026 at 02:25:43PM +0800, Liao Xuan wrote:
> Add support for dynamically adjusting the PCIe link rate of NVMe
> devices based on I/O activity. The link is downgraded to a
> configurable minimum rate during periods of low activity to save
> power, and upgraded to the maximum supported rate as soon as the
> workload exceeds a computed threshold, so that peak performance is
> maintained under load.
Pretty sure PCIe ASPM L1 states would save more power than downgrading
the link rate, as well as have better entry/exit latency than a software
driven monitor and link retrain.
next prev parent reply other threads:[~2026-11-03 19:08 UTC|newest]
Thread overview: 4+ messages / expand[flat|nested] mbox.gz Atom feed top
[not found] <cover.1790134954.git.liaoxuan@open-hieco.net>
2026-11-03 6:25 ` Liao Xuan
2026-11-03 18:23 ` Bjorn Helgaas
2026-11-03 19:08 ` Keith Busch [this message]
2026-09-24 6:15 [PATCH 0/3] Add adaptive NVMe " Liao Xuan
2026-09-24 6:15 ` [PATCH 1/3] nvme: Add adaptive PCIe " Liao Xuan
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