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charset=utf-8 Content-Disposition: inline Content-Transfer-Encoding: 8bit In-Reply-To: <20261003200132.866240-3-michal@nozomi.space> X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/293.791.62 Hi Michał, On 03.10.2026 22:01, Michał Kopeć wrote: > On MediaTek SoCs the GPU timestamp counter is fed by the SoC system timer > only once the TOP_TSVALUEB enable bits are set in the MFGCFG block. The > setting is lost whenever the GPU power domain is turned off. > > Without it, GPU_TIMESTAMP reads zero, so the SYSTEM_TIMESTAMP query and > timestamps written by jobs are always zero, which breaks timestamp > queries in userspace drivers. > > Look up the MFGCFG block from the mediatek,mfgcfg phandle and set the > bits from the vendor quirk hook, which runs on every power-up, as the > downstream kbase driver does. Without the phandle nothing changes. To me this looks like the right location for the fix inside the quirk function further below is somewhere in MT8188's device RPM handlers themselves, rather the Panfrost driver. RPM core keeps a tree of runtime dependencies, so SoC resume handlers would always be run before those of the child nodes (Panfrost being among them). > Signed-off-by: Michał Kopeć > --- > drivers/gpu/drm/panfrost/panfrost_device.h | 1 + > drivers/gpu/drm/panfrost/panfrost_drv.c | 1 + > drivers/gpu/drm/panfrost/panfrost_gpu.c | 39 ++++++++++++++++++++++ > drivers/gpu/drm/panfrost/panfrost_gpu.h | 1 + > 4 files changed, 42 insertions(+) > > diff --git a/drivers/gpu/drm/panfrost/panfrost_device.h b/drivers/gpu/drm/panfrost/panfrost_device.h > index 1fe1554f2652b..0a73939a023c3 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_device.h > +++ b/drivers/gpu/drm/panfrost/panfrost_device.h > @@ -134,6 +134,7 @@ struct panfrost_device { > int mmu_irq; > > void __iomem *iomem; > + struct regmap *mtk_mfgcfg; > struct clk *clock; > struct clk *bus_clock; > struct clk *bus_ace_clock; > diff --git a/drivers/gpu/drm/panfrost/panfrost_drv.c b/drivers/gpu/drm/panfrost/panfrost_drv.c > index 70c05210ea846..e811652e2384d 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_drv.c > +++ b/drivers/gpu/drm/panfrost/panfrost_drv.c > @@ -1133,6 +1133,7 @@ static const struct panfrost_compatible mediatek_mt8188_data = { > .pm_domain_names = mediatek_pm_domains, > .pm_features = BIT(GPU_PM_CLK_DIS) | BIT(GPU_PM_VREG_OFF), > .gpu_quirks = BIT(GPU_QUIRK_FORCE_AARCH64_PGTABLE), > + .vendor_quirk = panfrost_gpu_mt8188_quirk, > }; > > static const struct panfrost_compatible mediatek_mt8192_data = { > diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.c b/drivers/gpu/drm/panfrost/panfrost_gpu.c > index 29ac0dce5ff89..971abc9cc222c 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_gpu.c > +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.c > @@ -9,8 +9,11 @@ > #include > #include > #include > +#include > +#include > #include > #include > +#include > > #include > > @@ -114,6 +117,40 @@ void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev) > gpu_write(pfdev, GPU_PWR_OVERRIDE1, 0xfff | (0x20 << 16)); > } > > +#define MTK_MFG_TIMESTAMP 0x130 > +#define MTK_MFG_TIMESTAMP_TOP_TSVALUEB_EN 0x3 > + > +void panfrost_gpu_mt8188_quirk(struct panfrost_device *pfdev) > +{ > + /* > + * The GPU timestamp counter only counts once MFGCFG routes the SoC > + * system timer to it. The setting is lost whenever the GPU power > + * domain is turned off, so it has to be restored on every power-up. > + */ > + if (pfdev->mtk_mfgcfg) > + regmap_write(pfdev->mtk_mfgcfg, MTK_MFG_TIMESTAMP, > + MTK_MFG_TIMESTAMP_TOP_TSVALUEB_EN); > +} Here you cast an SoC issue as a GPU quirk, which is a misrepresentation of the problem. GPU quirks are about working around GPU-model specific issues by poking GPU registers themselves. > +static void panfrost_gpu_get_mtk_mfgcfg(struct panfrost_device *pfdev) > +{ > + struct device_node *np; > + struct regmap *regmap; > + > + np = of_parse_phandle(pfdev->base.dev->of_node, "mediatek,mfgcfg", 0); > + if (!np) > + return; > + > + regmap = device_node_to_regmap(np); > + of_node_put(np); > + if (IS_ERR(regmap)) { > + dev_warn(pfdev->base.dev, "failed to get MFGCFG: %pe\n", regmap); > + return; > + } > + > + pfdev->mtk_mfgcfg = regmap; > +} > + > static void panfrost_gpu_init_quirks(struct panfrost_device *pfdev) > { > u32 quirks = 0; > @@ -519,6 +556,8 @@ int panfrost_gpu_init(struct panfrost_device *pfdev) > { > int err; > > + panfrost_gpu_get_mtk_mfgcfg(pfdev); We cannot add SoC-specific workarounds in generic driver code. There has to be another way. > err = panfrost_gpu_soft_reset(pfdev); > if (err) > return err; > diff --git a/drivers/gpu/drm/panfrost/panfrost_gpu.h b/drivers/gpu/drm/panfrost/panfrost_gpu.h > index b4fef11211d5f..2b974576b96e9 100644 > --- a/drivers/gpu/drm/panfrost/panfrost_gpu.h > +++ b/drivers/gpu/drm/panfrost/panfrost_gpu.h > @@ -23,5 +23,6 @@ unsigned long long panfrost_cycle_counter_read(struct panfrost_device *pfdev); > unsigned long long panfrost_timestamp_read(struct panfrost_device *pfdev); > > void panfrost_gpu_amlogic_quirk(struct panfrost_device *pfdev); > +void panfrost_gpu_mt8188_quirk(struct panfrost_device *pfdev); > > #endif > -- > 2.55.0 Adrian Larumbe