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X-MS-Exchange-AntiSpam-MessageData-ChunkCount: 1 X-MS-Exchange-AntiSpam-MessageData-0: =?us-ascii?Q?Q2JKDzOFjzGd8292a2Wh8thkEr/WQ6HM62El4oAwIEMEAJtauJL5Xahgp9yX?= =?us-ascii?Q?POvFr3aBybbBa4hmxj6NFUOLgSi3f27vD+1id/O3HOtu9va4lp1eV38z5uKK?= =?us-ascii?Q?suL7xN46cQWzi9o8i3WULV3cRy9+lKpHj7IFWX/AuJLOs1DiRLM8FznhqBOW?= =?us-ascii?Q?fzN/67R/IAiOT7dguKf06bMnIEnC2rFlzSm1DIck20DxbqgXBZDuI5VyCqvB?= =?us-ascii?Q?O/QNdHgSXFJSFMKD4twZU1PjeRghjFyNkMFltlm61lEHCM5JWJm0+dHUKOmG?= =?us-ascii?Q?+RfD/0O1R6l924vIDGhjmHqFGM7a/gQaJgf0XnFvS+hCpsVXRZtMFuU6H+gN?= =?us-ascii?Q?AGlyB1xeXTL4ToliP15K551mL6gQq0frDIXoy3F5eTVdzxx2CkRtmaGwxotO?= =?us-ascii?Q?bs/isHlxn05+ZOisa/vo+teqAaQ0V74/1P1kq+qljp0bYKqt8dxgLuxVqp/j?= =?us-ascii?Q?e6+UF9UF+0l4LZNkzXXWW3GF0qA/2WBY6L4cszvjl6cSYqa9lDMTcSXW0IKD?= =?us-ascii?Q?eQMFSXZLXQVRHJCeVXtrSDODHlt1KlH2juTn6bV5XdeAGL6WNibmp2zuSqvt?= =?us-ascii?Q?Q5zqckAnEaJYMwUOYca4yVO4SO/UWh5k9+yeq0NvB0N29fYutXCFjtXzwTgg?= =?us-ascii?Q?OI2rWRQDrIK3t39WsiV7TMOJuGLcuEmgIpp5hFhyij9iiGkaQ6EOZLT9/G8u?= =?us-ascii?Q?oiwbNrP6WPcbmBf+hx9Qpj/h1Ny49MX+nZUqZQo0T3n0l1wkOeGDltgg5L7c?= =?us-ascii?Q?mmG4mvMekusTzOVSKq8Vl1fajcbBi6Dr2WVXUJGJprbAp/TyOMb28OMbVy8I?= =?us-ascii?Q?LdOc3pS/MxRtXrez8aX74ODLjqFYCmBzTrUizmtt7b9LW0MfAukneMQrQJlM?= =?us-ascii?Q?u5FJXEKx/yjCWAfSKiALiDA9Pg2vay5GY/Qm2Cs63QGjgG+zX6TO45rf9I3I?= =?us-ascii?Q?HPZ9DR2GIBn5T41rTUUykMJbTTYA2p1K3WBrpiiaydcOvuB3ryHN78u/sUK3?= =?us-ascii?Q?wKSgeeG++h/c1JIHZ3bcyeMBKDR6cSaHFRXDgpAeHdPXsJepYLA0WgtFTek0?= =?us-ascii?Q?Bj7zd0sbKPC+fTK4MwOWoBqJV16UnFwyKRaIJoopVgk81DSEI0McthDTo48p?= =?us-ascii?Q?x7pUOD0uu58iXgPdyly/Ctk2Ns2XKfWgfRdbEATvM6004zwBVXDQ21HtoNR6?= =?us-ascii?Q?p/uowd5E4jm0T30AgbCgQEF13haooL2ndWDFBDq1XG6WF0XIrcZZDDmaalc4?= =?us-ascii?Q?0iUyzMLaXBlsvAMZr3/WxMQ7zB7mxfFOn2USILq9c++Ugzh5nVQbXqgYUVWI?= =?us-ascii?Q?DFu+0cJswSVENplmdvPTKUt1yMdFrPdJUMOcC207b52LdOtJFxM+/P9glaV6?= =?us-ascii?Q?/q7ntR2/SGwtAU3B0uP/NtSuy6ANsHvTA0+IItNSPgvZtQpcskYn7zMWoT4t?= =?us-ascii?Q?7hiqFUQ7Y7eAluLQca+OYhRBatK3BS3BgVd5zxraYbh4AvnHY2+1XRh13oQH?= =?us-ascii?Q?k6YMKRGCqyF52K5lD7SJQkmXc3t0RYHK/nXZu3WN4Jf8oWj+Z6qhDxLjvU7g?= =?us-ascii?Q?8FmEyPsB/DR5EWtE7ZYAECNkIGRaA6pmxMx5vhEkljulWJTA/XCSJGm0Swas?= =?us-ascii?Q?34/gt3UxwD2qi0tP+SSAMpUA0sF4wIbQnjX2LkbK4nbPdOdvJOoX27c1esp1?= =?us-ascii?Q?taA9LVzvtknYFZK3Gf60hrgkYOUUjnzlYV6IGXxqu+stPaXULWnun+OoS3iz?= =?us-ascii?Q?l/9K0XnQbF498XmJdcVUTdklBlbFbd8wI+INOD4s+j85vvbbv6Qh?= X-OriginatorOrg: oss.nxp.com X-MS-Exchange-CrossTenant-Network-Message-Id: 10a3d5d3-73e5-42c1-16fc-08df3a997d2b X-MS-Exchange-CrossTenant-AuthSource: MI3PR04MB12438.eurprd04.prod.outlook.com X-MS-Exchange-CrossTenant-AuthAs: Internal X-MS-Exchange-CrossTenant-OriginalArrivalTime: 04 Nov 2026 17:31:41.5962 (UTC) X-MS-Exchange-CrossTenant-FromEntityHeader: Hosted X-MS-Exchange-CrossTenant-Id: 686ea1d3-bc2b-4c6f-a92c-d99c5c301635 X-MS-Exchange-CrossTenant-MailboxType: HOSTED X-MS-Exchange-CrossTenant-UserPrincipalName: iB06nKMcdhpaDr43NpX+kyu7cy4Ukcevt1+n6B7KVBRTnG7ID8KNssFDbL+FM9TbfDS40Z0rhcmQbsGWTIR1kHV7Fh9QNgXjeTGwjX3NhbgBVp6PEpp4VuYGJOn0HbL/ X-MS-Exchange-Transport-CrossTenantHeadersStamped: MI9PR04MB043780 On Thu, Nov 05, 2026 at 01:12:25AM +0900, Koichiro Den wrote: > While HDMA is running, DMA_LLP is updated only at watermark events. > Enable watermark interrupts to track progress without waiting for the > channel to stop. > > Set the watermark bits on entries that request an interrupt, configure > local or remote delivery, and pass events to the LL progress handler. > Unmask local watermark interrupts only for LL channels in local IRQ mode. > > Signed-off-by: Koichiro Den > --- Reviewed-by: Frank Li > Changes from v6: > - Keep watermark interrupts masked for non-LL channels (Sashiko). > - Link to v6: https://lore.kernel.org/r/20261030150742.2586776-4-den@valinux.co.jp/ > > Note: Since v6, IRQ placement has been limited to descriptor ends and > the last free entry to keep the series small. Further tuning can > be done in follow-up patches. I should've mentioned this in v6 > when dropping v5 patch 14: > https://lore.kernel.org/r/20260812155721.2807506-15-den@valinux.co.jp/ > > drivers/dma/dw-edma/dw-hdma-v0-core.c | 62 ++++++++++++++++++++++----- > drivers/dma/dw-edma/dw-hdma-v0-regs.h | 1 + > 2 files changed, 52 insertions(+), 11 deletions(-) > > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-core.c b/drivers/dma/dw-edma/dw-hdma-v0-core.c > index aa430219d0af..0cccd0003a1b 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-core.c > +++ b/drivers/dma/dw-edma/dw-hdma-v0-core.c > @@ -58,7 +58,8 @@ static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val) > { > val &= ~(HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_REMOTE_ABORT_INT_EN | > HDMA_V0_LOCAL_STOP_INT_EN | HDMA_V0_REMOTE_STOP_INT_EN | > - HDMA_V0_ABORT_INT_MASK | HDMA_V0_STOP_INT_MASK); > + HDMA_V0_ABORT_INT_MASK | HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_STOP_INT_MASK); > > /* > * HDMA_INT_STATUS.STOP and .ABORT are latched only when LSIE and > @@ -68,6 +69,9 @@ static u32 dw_hdma_v0_core_int_setup(struct dw_edma_chan *chan, u32 val) > */ > val |= HDMA_V0_LOCAL_ABORT_INT_EN | HDMA_V0_LOCAL_STOP_INT_EN; > > + if (chan->non_ll || chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) > + val |= HDMA_V0_WATERMARK_INT_MASK; > + > if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) > val |= HDMA_V0_REMOTE_ABORT_INT_EN | > HDMA_V0_REMOTE_STOP_INT_EN | > @@ -81,10 +85,12 @@ static void dw_hdma_v0_core_ch_off(struct dw_edma *dw, enum dw_edma_dir dir, > u16 id) > { > SET_CH_32(dw, dir, id, int_setup, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > SET_CH_32(dw, dir, id, ch_en, 0); > SET_CH_32(dw, dir, id, int_clear, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > } > > static void dw_hdma_v0_core_off(struct dw_edma *dw) > @@ -95,18 +101,26 @@ static void dw_hdma_v0_core_off(struct dw_edma *dw) > dir = EDMA_DIR_WRITE; > for (id = 0; id < dw->wr_ch_cnt; id++) { > SET_CH_32(dw, dir, id, int_setup, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | > + HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > SET_CH_32(dw, dir, id, int_clear, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | > + HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > SET_CH_32(dw, dir, id, ch_en, 0); > } > > dir = EDMA_DIR_READ; > for (id = 0; id < dw->rd_ch_cnt; id++) { > SET_CH_32(dw, dir, id, int_setup, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | > + HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > SET_CH_32(dw, dir, id, int_clear, > - HDMA_V0_STOP_INT_MASK | HDMA_V0_ABORT_INT_MASK); > + HDMA_V0_STOP_INT_MASK | > + HDMA_V0_WATERMARK_INT_MASK | > + HDMA_V0_ABORT_INT_MASK); > SET_CH_32(dw, dir, id, ch_en, 0); > } > } > @@ -168,6 +182,14 @@ static void dw_hdma_v0_core_clear_done_int(struct dw_edma_chan *chan) > SET_CH_32(dw, chan->dir, chan->id, int_clear, HDMA_V0_STOP_INT_MASK); > } > > +static void dw_hdma_v0_core_clear_watermark_int(struct dw_edma_chan *chan) > +{ > + struct dw_edma *dw = chan->dw; > + > + SET_CH_32(dw, chan->dir, chan->id, int_clear, > + HDMA_V0_WATERMARK_INT_MASK); > +} > + > static void dw_hdma_v0_core_clear_abort_int(struct dw_edma_chan *chan) > { > struct dw_edma *dw = chan->dw; > @@ -208,17 +230,23 @@ dw_hdma_v0_core_handle_int(struct dw_edma_irq *dw_irq, enum dw_edma_dir dir, > continue; > > val = dw_hdma_v0_core_status_int(chan); > - if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) { > + > + if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) > dw_hdma_v0_core_clear_done_int(chan); > - handler(chan, DW_EDMA_IRQ_STOP); > + if (FIELD_GET(HDMA_V0_WATERMARK_INT_MASK, val)) > + dw_hdma_v0_core_clear_watermark_int(chan); > > + if (FIELD_GET(HDMA_V0_STOP_INT_MASK, val)) { > + handler(chan, DW_EDMA_IRQ_STOP); > + ret = IRQ_HANDLED; > + } else if (FIELD_GET(HDMA_V0_WATERMARK_INT_MASK, val)) { > + handler(chan, DW_EDMA_IRQ_PROGRESS); > ret = IRQ_HANDLED; > } > > if (FIELD_GET(HDMA_V0_ABORT_INT_MASK, val)) { > dw_hdma_v0_core_clear_abort_int(chan); > handler(chan, DW_EDMA_IRQ_ABORT); > - > ret = IRQ_HANDLED; > } > } > @@ -275,7 +303,7 @@ static void dw_hdma_v0_core_ch_enable(struct dw_edma_chan *chan) > > /* Enable engine */ > SET_CH_32(dw, chan->dir, chan->id, ch_en, BIT(0)); > - /* Interrupt unmask - stop, abort */ > + /* Interrupt unmask - stop, watermark, abort */ > tmp = GET_CH_32(dw, chan->dir, chan->id, int_setup); > tmp = dw_hdma_v0_core_int_setup(chan, tmp); > SET_CH_32(dw, chan->dir, chan->id, int_setup, tmp); > @@ -336,6 +364,11 @@ static void dw_hdma_v0_core_ch_config(struct dw_edma_chan *chan) > /* MSI done addr - low, high */ > SET_CH_32(dw, chan->dir, chan->id, msi_stop.lsb, chan->msi.address_lo); > SET_CH_32(dw, chan->dir, chan->id, msi_stop.msb, chan->msi.address_hi); > + /* MSI watermark addr - low, high */ > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.lsb, > + chan->msi.address_lo); > + SET_CH_32(dw, chan->dir, chan->id, msi_watermark.msb, > + chan->msi.address_hi); > /* MSI abort addr - low, high */ > SET_CH_32(dw, chan->dir, chan->id, msi_abort.lsb, chan->msi.address_lo); > SET_CH_32(dw, chan->dir, chan->id, msi_abort.msb, chan->msi.address_hi); > @@ -355,6 +388,13 @@ dw_hdma_v0_core_ll_data(struct dw_edma_chan *chan, struct dw_edma_burst *burst, > if (cb) > control |= DW_HDMA_V0_CB; > > + if (irq) { > + control |= DW_HDMA_V0_LWIE; > + > + if (chan->irq_mode == DW_EDMA_CH_IRQ_REMOTE) > + control |= DW_HDMA_V0_RWIE; > + } > + > dw_hdma_v0_write_ll_data(chan, idx, control, burst->sz, burst->sar, > burst->dar); > } > diff --git a/drivers/dma/dw-edma/dw-hdma-v0-regs.h b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > index b88226cdd791..e240ffb3dea7 100644 > --- a/drivers/dma/dw-edma/dw-hdma-v0-regs.h > +++ b/drivers/dma/dw-edma/dw-hdma-v0-regs.h > @@ -18,6 +18,7 @@ > #define HDMA_V0_LOCAL_STOP_INT_EN BIT(4) > #define HDMA_V0_REMOTE_STOP_INT_EN BIT(3) > #define HDMA_V0_ABORT_INT_MASK BIT(2) > +#define HDMA_V0_WATERMARK_INT_MASK BIT(1) > #define HDMA_V0_STOP_INT_MASK BIT(0) > #define HDMA_V0_LINKLIST_EN BIT(0) > #define HDMA_V0_CONSUMER_CYCLE_STAT BIT(1) > -- > 2.54.0 >