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micalg=pgp-sha512; protocol="application/pgp-signature"; boundary="kdkht52zgzkidek7" Content-Disposition: inline In-Reply-To: X-Zoho-Virus-Status: 1 X-Zoho-AV-Stamp: zmail-av-0.2.13.1.5.4/293.861.93 X-ZohoMailClient: External --kdkht52zgzkidek7 Content-Type: text/plain; protected-headers=v1; charset=us-ascii Content-Disposition: inline Content-Transfer-Encoding: quoted-printable Subject: Re: [PATCH v8 7/9] PCI: dw-rockchip: Add pme_turn_off support MIME-Version: 1.0 Hi, On Thu, Nov 05, 2026 at 08:51:14AM +0800, Shawn Lin wrote: > [...] > > +static void rockchip_pcie_pme_turn_off(struct dw_pcie_rp *pp) > > +{ > > + struct dw_pcie *pci =3D to_dw_pcie_from_pp(pp); > > + struct rockchip_pcie *rockchip =3D to_rockchip_pcie(pci); > > + struct device *dev =3D rockchip->pci.dev; > > + u32 status; > > + int ret; > > + > > + /* 1. Broadcast PME_Turn_Off Message, bit 4 self-clear once done */ > > + rockchip_pcie_writel_apb(rockchip, PME_TURN_OFF, PCIE_CLIENT_MSG_GEN); > > + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_MSG_GEN, > > + status, !(status & BIT(4)), PCIE_PME_TO_L2_TIMEOUT_US / 10, > > + PCIE_PME_TO_L2_TIMEOUT_US); > > + if (ret) { > > + dev_warn(dev, "Failed to send PME_Turn_Off\n"); > > + return; > > + } > > + > > + /* 2. Wait for PME_TO_Ack, bit 9 will be set once received */ > > + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_INTR_STAT= US_MSG_RX, > > + status, status & BIT(9), PCIE_PME_TO_L2_TIMEOUT_US / 10, > > + PCIE_PME_TO_L2_TIMEOUT_US); > > + if (ret) { > > + dev_warn(dev, "Failed to receive PME_TO_Ack\n"); > > + return; > > + } > > + > > + /* 3. Clear PME_TO_Ack and Wait for ready to enter L23 message */ > > + rockchip_pcie_writel_apb(rockchip, PME_TO_ACK, PCIE_CLIENT_INTR_STATU= S_MSG_RX); > > + ret =3D readl_poll_timeout(rockchip->apb_base + PCIE_CLIENT_POWER_CON, > > + status, status & PME_READY_ENTER_L23, > > + PCIE_PME_TO_L2_TIMEOUT_US / 10, > > + PCIE_PME_TO_L2_TIMEOUT_US); > > + if (ret) > > + dev_err(dev, "Failed to get ready to enter L23 message\n"); > > +} >=20 > This is a question for the DWC core: should we change > dw_pcie_host_ops::pme_turn_off() to return a value instead of silently > ignoring a failure? >=20 > Looking at pcie-designware-host.c, we have: >=20 > if (pci->pp.ops->pme_turn_off) { > pci->pp.ops->pme_turn_off(&pci->pp); > } else { > ret =3D dw_pcie_pme_turn_off(pci); > if (ret) > return ret; > } >=20 > The handling feels asymmetric. If ->pme_turn_off fails, shouldn't we abort > dw_pcie_suspend_noirq as well? That sounds sensible to me. I had a look and apart from Rockchip, Layescape can run into an error. Most platforms cannot produce any errors in that function, which explains why this was void to begin with. > Other than that, this patch looks good to me in current shape, > Reviewed-by: Shawn Lin Thanks, taken over for v9. > We can further discuss the callback's return value issue on top. Agreed. This will touch all the glue drivers to add a return 0. I think its better to do that in a separate series. Greetings, -- Sebastian --kdkht52zgzkidek7 Content-Type: application/pgp-signature; name="signature.asc" -----BEGIN PGP SIGNATURE----- iQIzBAABCgAdFiEE72YNB0Y/i3JqeVQT2O7X88g7+poFAmrsaqkACgkQ2O7X88g7 +ppOQQ//WoZHIiRbMmXqisCxBjqzqieSnrTn+4gdKBb5ipuBqtBM3YnhR5D9z8vj qxkO9v5mR2ykXKTUTN0b/IgpGwxVnC5ccoYNQWNzpIttV4i/e1Tj7V+4KyGnxfo9 ZI+qDp3y2jGlsh7j89VTZmHoH78j8CLDDGZqUAIhW+sFNvqyJ69abnG8c6ozO6Yu R4yjEHkEdan4+RJJufB+9hCzbLAJs3OgZkJMbUf1DkVgLxtJGmRp91M+ZcNqlmo1 H9ri2ur38nBzAhcgQqAIl3FbqdS42WI8EIbB0nUT+u6P9UGw3Run7NyNmSl9SZO9 cimqFBsGEJP19fcWYsaY52FpYHapPlkTvL961G74cIZaXeHhgOU+np3vlKu6L9Nj CYVktU59FVlyL2AjLNxPPz7Nj0ApJwWqeHduV5iv6mPXwZKsgfBlljKKmt9ENEV4 3aXWLthxSTXn8EbUJaDhbCEuSAckZ6Q0jBLLm1jxI6Xl91BXLugGeHrxHLg7Ot/W eItpBHYxgVmFYdqWIOEnwEvNosQ5AAGuiaxxpbtiijQ1Ry2cgD2WwQ3eIxPRhI8X mSmeonaUh1lDbY6pJlb+R8O1lADwOTreUVYahV3BleF6YiVCqe18qJPXu+Vw/Oul lElhNe92o+6baSESkxZHh9syJgR8/81Pz8CGQ+SjICYIzN+M+iA= =4x0q -----END PGP SIGNATURE----- --kdkht52zgzkidek7--